Altera Corporation

Tat Mun Lui

Boon Jin Ang

Zun Yang Tan

Chiang Wei Lee

Want Sent Khor

Richard Jin Guan Saw

Kar Keng Chua

Wei Yee Koay

Jun Pin Tan

Ting Lok Song

Bee Yee Ng

Thow Pang Chong

Eu Geen Chew

Kam Fai Suit

One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.

Integrated circuit with dynamically-adjustable buffer space for serial interface

A method of operating an integrated circuit may include receiving an update request via an input-output protocol, such as the Peripheral Interconnect Component Express (PCIe) protocol. The integrated circuit is placed in an update mode when the update request is received. State information is stored in predefined registers on the integrated circuit and configuration data on the integrated circuit may be subsequently updated. An asserted update mode signal is stored in a status register on the integrated circuit to indicate that the integrated circuit is in the update mode. The configuration data may include a core configuration portion and a peripheral configuration portion. When the integrated circuit is in the update mode, only the core configuration is updated while the peripheral configuration portion may be preserved.

Circuitry and techniques for updating configuration data in an integrated circuit

Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

Configurable memory block

A delay circuit that includes a first delay cell oriented in a first orientation and a second delay cell oriented in a second orientation is described. In one embodiment, the first orientation is perpendicular to the second orientation. More specifically, in one embodiment, the first orientation is vertical and the second orientation is horizontal.

Delay circuit with delay cells in different orientations

In circuitry such as a programmable logic device ('PLD'), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate ('MAC') capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.

Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices

Growing community of inventors

Petaling Jaya, Malaysia

Tat Mun Lui