Renesas Electronics Corporation

Nec Electronics Corporation

Taro Moriya

Satoshi Uchiya

Hiroyoshi Kudou

Hiroaki Katou

Yasutaka Nakashiba

Masayuki Furumiya

Hiroshi Yanagigawa

Kazuhisa Mori

A semiconductor device has a silicon film for a diode formed on a semiconductor substrate via an insulating film, and first and second wirings formed on an upper layer of the silicon film. The silicon film has a p-type silicon region and a plurality of n-type silicon regions, and each of the plurality of n-type silicon regions is surrounded by the p-type silicon region in a plan view. The p-type silicon region is electrically connected to the first wiring, and the plurality of n-type silicon regions are electrically connected to the second wiring.

Semiconductor device and method of manufacturing the same

A semiconductor device for suppressing a variation in characteristics caused by a current flowing at the time of breakdown is disclosed. The first power MOS transistor Qand the column CLM are formed in the first element region FCM defined in the epitaxial layer NEL, and the second power MOS transistor Qis formed in the second element region RCM. The first power MOS transistor Qincludes a first trench gate electrode TGE, and the second power MOS transistor Qincludes a second trench gate electrode TGE. The depth GDPof the first trench gate electrode TGEis shallower than the depth GDPof the second trench gate electrode TGE

A semiconductor device includes a semiconductor substrate, a gate electrode, and a first contact plug. The semiconductor substrate includes a first surface and a second surface. Over the semiconductor substrate, a source region, a drain region, a drift region, and a body region are formed. A first trench in which the gate electrode is buried is formed in the first surface. The first surface includes an effective region and a peripheral region. The first trench extends from the peripheral region over the effective region along a first direction. The gate electrode includes a portion opposed to and insulated from the body region sandwiched between the source region and the drift region. In the peripheral region, the first contact plug is electrically coupled to the gate electrode buried in the first trench such that its longer side is along the first direction when seen in a plan view.

To provide a semiconductor device less affected by noise without making a manufacturing process more complicated and increasing a chip area. The device has a semiconductor substrate having first and second surfaces, a first-conductivity-type drain region on the second surface side in the semiconductor substrate, a first-conductivity-type drift region on the first surface side of a substrate region, a second-conductivity-type base region on the first surface side of the drift region, a first-conductivity-type source region on the first surface of the semiconductor substrate sandwiching a base region between the source and drift regions, a gate electrode opposite to and insulated from the base region, a wiring on the first main surface electrically coupled to the source region, and a first conductive film on the first main surface, opposite to and insulated from the wiring, and electrically coupled to the substrate region.

Semiconductor device and method of manufacturing same

An n-channel power MOS transistor having a gate electrode is formed in an element formation region defined in a semiconductor substrate. A p-type guard ring region is formed in a terminal region. A plurality of p-type column regions are formed from the bottom of the p-type base region to a further deeper position. The column region located in the outermost periphery and the p-type guard ring region are spaced apart from each other by a distance. A gate electrode lead-out portion electrically coupled to the gate electrode is formed in the p-type guard ring region.

Semiconductor device including power MOS transistor

Trenches are formed in a base layer and extend parallel to each other. A gate insulating film is formed on the inner wall of each of multiple trenches. A gate electrode GE is buried in each of the trenches. The source layer is formed in the base layer to a depth less than the base layer. The source layer is disposed between each of the trenches. A second conduction type high concentration layer is formed between the source layer and the trench in a plan view. The trench, the source layer, and the second conduction type high concentration are arranged in this order repetitively in a plan view. One lateral side of the trench faces the source layer and the other lateral side of the trench faces the second conduction type high concentration layer.

Semiconductor device with gate electrodes buried in trenches

A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view.

Semiconductor device and manufacturing method thereof

A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.

Semiconductor device and method for manufacturing the same

A reticle includes a repetition pattern and a peripheral pattern, one of which has a first side in a first direction and the other a second side in the first direction. The first side has a first length that is n times the second length of the second side, where n is an integer equal to or larger than 1. The first pattern has at least one of first misalignment measurement patterns provided at positions distant by a third length and ((the third length)+(n&#x2212;1).times.(the second length)) from an upper end of the first pattern. The third length is equal to or smaller than the second length. The second pattern has a second misalignment measurement pattern provided at a position distant by the third length from an upper end of the second pattern.

Reticle and manufacturing method of solid-state image sensor

A reticle includes: a repetition pattern; and a peripheral pattern. One of the repetition pattern and peripheral pattern is a first pattern with a first side in a first direction and the other is a second pattern with a second side in the first direction. The first side has a first length equal to or longer than a second length of the second side. The first length is n (n is an integer equal to or larger than 1) times as large as the second length. The first pattern has at least one of first misalignment measurement patterns provided at positions distant by a third length and ((the third length)+(n&#x2212;1)&#xd7;(the second length)) from an upper end of the first pattern. The third length is equal to or smaller than the second length. The second pattern has a second misalignment measurement pattern provided at a position distant by the third length from an upper end of the second pattern.

A pad structureincludes an electrode pad (a first electrically conducting filmand a second electrically conducting film) and an insulating film provided over a peripheral region of the electrode pad so as to surround the electrode pad, and the insulating film has a structure including a protective film (a cover oxide film) and a transparent resin film (a transparent resin) provided on the cover oxide film

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Kanagawa, Japan

Taro Moriya