Sanken Electric Co., Ltd.

Allegro Microsystems, LLC

Polar Semiconductor, Inc.

Taro Kondo

Shunsuke Fukunaga

Shinji Kudo

Shinji Kudoh

Bungo Tanaka

Jun Yasuhara

A semiconductor device is disclosed including a sub-layer with first conductivity type, a drift layer with first conductivity type, a base region with second conductivity type positioned on the drift layer, a source region in contact with the base region, a source electrode, a plurality of trenches, at least one of the trenches in contact with the drift layer, the base region, and the source region, a plurality of insulating regions, at least one of the insulating regions positioned inside of each trench, a plurality of gate electrodes, at least one of the gate electrodes positioned inside of each trench; and a plurality of field plates, at least one of the field plates electrically connected to the source electrode and positioned in the insulating region in the trench. The field plate comprises high-resistance polysilicon.

Semiconductor device

A semiconductor is disclosed that may include: a first drift region; a base region arranged on the first semiconductor layer; a source region arranged on the base region; a main electrode electrically connected to the source region; and a gate electrode structure that penetrates the source region and base region and reaches the first drift region, wherein the gate electrode structure comprises: a gate electrode; and an insulating material that insulates the gate electrode from the first drift region and the base region; and a field plate structure reaching the first drift region deeper than the gate electrode structure, wherein the field plate structure comprises: a field plate; a resistive part that electrically connects the main electrode to the field plate; and an insulating material that insulates the field plate and the resistive part section from the first drift region and the base region.

A semiconductor device is disclosed that includes a group of trenches positioned in active region inside a first semiconductor region. A first trench is positioned in an outer peripheral region on an outer side of an active region. A second trench is positioned on an outer side of the first trench positioned in the outer peripheral region on the outer side of the active region. A mesa portion is positioned between the first and the second trenches. An insulating layer is positioned inside the first and second trenches. A second field plate is positioned inside the insulating layer in the first trench. A third field plate positioned inside the second insulating layer in the second trench. The mesa portion includes the semiconductor region electrically coupled to the first main electrode on an outermost side. The first trench does not have the gate electrode at upper part of the first trench.

Semiconductor device having a group of trenches in an active region and a mesa portion

A semiconductor device includes: a semiconductor base; a trench insulating film which is provided on the inner wall surface of a trench formed from the upper surface of the semiconductor base in a film thickness direction of the semiconductor base and including a charged region which is charged positively; and a gate electrode provided on the trench insulating film within the trench. The positive charge density of the charged region at least in a side part of an outer region of the trench insulating film which is provided on the side surface of the trench is higher than that of an inner region of the trench insulating film which is opposite to the outer region, the outer region being in contact with the semiconductor base.

A semiconductor device includes: a semiconductor basein which a first trenchis formed in a mesh-like shape in a plan view and a second trenchis formed in a mesh opening surrounded by the first trench; a first semiconductor elementwhich is formed in the semiconductor baseand includes a first gate electrodeprovided within the first trench; and a second semiconductor elementwhich is formed in the semiconductor baseand includes a second gate electrodeprovided within the second trenchsurrounded by the first gate electrode

A semiconductor device in embodiments, may include a device region having: two active trenches, each having at least a gate electrode. Two insulated trenches each having an electrode may be formed between the two active trenches separated by a junction. First p-doped layers may be provided between a first active trench and a first insulated trench, and between a second active trenches and a second insulated trench. Second p-doped layers may be provided between a first insulated trench and a second insulated trench with the junction arranged therebetween. The second p-doped layers may be provided on an external surface of the respective first one and second one of the two insulated trenches at a depth and a thickness set to form a current path when the power semiconductor device is in an OFF state.

Vertical power MOSFET device having doped regions between insulated trenches and a junction arranged therebetween

A semiconductor device may comprise a substrate; a trench formed in the substrate and filled with an insulating layer; and a gate electrode and a source embedded in the insulating layer. The gate electrode and the source electrode may be positioned in the insulating layer in the trench above and below each other. From a cross-sectional perspective, the gate electrode and the source electrode are not overlapped in horizontal or vertical direction. The trench may extend to a first depth of a bottom surface of the trench below the gate electrode, and may extend to a second depth of the bottom surface of the trench below the source electrode. The first depth and the second depth may be different.

Semiconductor device having improved trench and electrode structures

A semiconductor device according to one or more embodiments may include: a drain region; a drift region positioned above the drain region; a base region positioned on the drift region; a trench positioned to abut the base region and the drift region; an insulating in the trench; a counter electrode embedded in the insulating film; a gate electrode positioned above the counter electrode and that is embedded in the insulating film; and a source region that abuts the base region and the trench, wherein a thickness of the insulating film between the gate electrode and an interface between the drift region and the base region is larger than a thickness of the insulating film between the gate electrode and an interface between the source region and the base region.

Semiconductor device having improved trench, source and gate electrode structures

A semiconductor device may include a device region having one or more active trenches, a field termination region having an edge trench. A depth of the edge trench is larger than a depth of the one or more active trenches. A thickness of an insulation layer in the edge trench is larger than a thickness of an insulation layer in the one or more active trenches. In some embodiments, the first depth is from 1.2 to 2.0 times larger than the second depth, and a first width of the edge trench is 1.5 to 4.0 times larger than a second width of the one or more active trenches. In a cross-sectional view, a gate electrode of the edge trench is laterally offset from the source electrode in a depth direction of the edge trench such that the gate electrode and the source electrode do not overlap.

Semiconductor device having improved edge trench, source electrode and gate electrode structures

A semiconductor device includes: three or more transistors, which are formed on a semiconductor substrate and arranged in one direction; and a PN junction diode, which is formed in a part of a region between the transistors, wherein the transistor includes: a trench, which is formed inwardly from a front surface; and a conductive region in the trench; wherein a first trench is a trench of the transistor which is not adjacent to the PN junction diode, and a second trench is a trench of one or both of the two transistors adjacent to the PN junction diode, wherein a bottom surface of the first trench is formed in a semiconductor region of a first impurity concentration, and wherein a bottom surface of the second trench is formed in a semiconductor region of a second impurity concentration, which is higher than the first impurity concentration.

A semiconductor device has a plurality of transistors, which have first electrodes in first trenches, and includes: two second trenches, which are formed side by side between the first trenches. A second electrode is formed in each of the two second trenches. A first impurity region is formed between the first trench and the second trench; a second impurity region is formed to abut on the first trench; a third impurity region is formed to abut on the second trench; a fourth impurity region, which is formed between two of the second trenches and has a higher impurity concentration than the first impurity region; and a fifth impurity region is formed below the first impurity region and the fourth impurity region. A third electrode is formed to be electrically connected to the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region.

A semiconductor device includes: a trench; a first electrode is formed in the trench; a first impurity region, which has a first conductivity type and is formed to abut on the trench; a second impurity region, which has a second conductivity type and is formed to abut the trench; an insulating film, which is formed on the front surface of the semiconductor substrate; a conductive plug, which is formed to penetrate through the insulating film and is electrically connected to the first impurity region and the second impurity region; wherein the conductive plug includes: a silicon layer made of silicon other than a single crystal; a silicide crystallite contained in the silicon layer; and a blocking layer that is formed to cover sides of the silicon layer and is made of a material that is impervious to the silicide crystallites.

A semiconductor device includes: a first semiconductor layer formed at a surface of a semiconductor substrate; an insulating layer formed on the surface of the semiconductor substrate; a first electrode that is electrically connected to the first semiconductor layer; a second semiconductor layer formed to a surface of a region, which is adjacent to the first semiconductor layer; a second electrode formed above a part of the second semiconductor layer; a third semiconductor layer adjacent to the second semiconductor layer in the one direction; a fourth semiconductor layer formed to a surface of a region, which is adjacent to the third semiconductor layer in the one direction; a third electrode that is electrically connected to the fourth semiconductor layer; and a conductor that is separated from the second electrode in the one direction and is kept at the same potential as the first electrode.

Growing community of inventors

Niiza, Japan

Taro Kondo