Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Taro Fujii

Masato Motomura

Takao Toi

Koichiro Furuta

Kenichiro Anjo

Toru Awashima

Katsumi Togawa

Noritsugu Nakamura

Toshirou Kitaoka

Hirokazu Kami

Teruhito Tanaka

Nobuki Kajihara

Takeshi Inuo

Tooru Awashima

Toshiro Kitaoka

Yoshikazu Yabe

Yoshinosuke Kato

Yoshitaka Izawa

Kouichiro Furuta

Ryoko Sasaki

Kouichirou Furuta

Yoshiyuki Miyazawa

A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

Semiconductor device including array of processor elements and method of controlling the same

A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.

Semiconductor device, data generation methods used for the same, and method of controlling the same

A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Semiconductor device and method of controlling the semiconductor device

A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.

Semiconductor device and control method thereof for processing

According to an embodiment, a reconfigurable deviceincludes a configuration information storage memory, a state transition management unit, and a data path unit. When a failure is not detected in either of tiles Tand Tprovided in the data path unit, the state transition management unitselects the configuration information item so that a first processing circuit is configured using the tiles Tand T, while when a failure is detected in the tile T, the state transition management unitselects the configuration information item so that after a first intermediate processing circuit is configured using the tile Tin which no failure is detected, a second intermediate processing circuit is configured again using the tile Tin order to achieve the first processing circuit.

A parallel arithmetic device includes a status management section, a plurality of processor elements, and a plurality of switch elements for determining the relation of coupling of each of the processor elements. Each of the processor elements includes an instruction memory for memorizing a plurality of operation instructions corresponding respectively to a plurality of contexts so that an operation instruction corresponding to the context selected by the status management section is read out, and a plurality of arithmetic units for performing arithmetic processes in parallel on a plurality of sets of input data in a manner compliant with the operation instruction read out from the instruction memory.

Parallel arithmetic device, data processing system with parallel arithmetic device, and data processing program

A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline.

Behavioral synthesis apparatus, behavioral synthesis method, data processing system including behavioral synthesis apparatus, and non-transitory computer readable medium storing behavioral synthesis program

A state transition management device includes a first terminal receiving a first signal based on a current state-number, a memory which stores a state transition rule and from which a plurality of subsequent state-number candidates are read out in accordance with the first signal, a plurality of first nodes revealing the plurality of subsequent state-number candidates, a second terminal receiving a second signal based on the current state-number, a selection method specifying unit which outputs a selection method specifying signal in accordance with the second signal, a second node revealing the selection method specifying signal, a event terminal receiving a event-signal based on an event, a third terminal receiving a third signal based on the current state-number, a selection circuit which selects a subsequent state-number from the plurality of subsequent number candidates in accordance with the event-signal and the third signal.

State transition management device and state transition management method thereof

A reconfigurable device comprises a plurality of processing elements, a main memory unit that stores plural pieces of circuit configuration information, a cache unit that caches circuit configuration information forwarded to at least one of the processing elements from the main memory unit, and a cache control unit that controls forwarding of circuit configuration information from the cache unit to the processing element. The cache control unit selects circuit configuration information which must be forwarded to each processing element. When the selected circuit configuration information is not stored in the cache unit, the cache control unit reads out the circuit configuration information from the main memory unit, stores the read-out circuit configuration information in the cache unit, and sends forward the circuit configuration information to the processing element from the cache unit.

Reconfigurable device

A state transition management device includes a memory that stores subsequent state number candidates for a current state number and a selection circuit that selects a subsequent state number from among the subsequent state number candidates that have been read out from the memory. For the state number having the subsequent state number candidates that are branch destinations of the current state number and are small in number, the memory stores the subsequent state number candidates for a plurality of current state numbers at one address in the memory that can be concurrently read out. The selection circuit selects the subsequent state number based on an event identification code () and a current state number.

State transition management device and method

A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N&#x2212;1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.

Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium

A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

Array-type processor having plural processor elements controlled by a state control unit

A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one operation unit or one memory unit. The plurality of function blocks each includes at least one data input port connected to at least on of the plurality of programmable switches and at least one data output port connected to at least one of the plurality of programmable switches. Further, at least a pair of function blocks included in the plurality of function blocks is connected without intervening the programmable switch and data being output from a direct output port included in one of the pair of function blocks can be input to a direct input port included in the other of the pair of function blocks.

Switch coupled function blocks with additional direct coupling and internal data passing from input to output to facilitate more switched inputs to second block

Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration information memory, and a buffer which is on-off controlled based on information stored in the configuration information memory and each of which controls connection between each of the functional blocks and each bus. When an error in the configuration information memory is detected by the error detection circuit, the buffer with an output thereof connected to the bus is set to an off-state, based on a result of error detection.

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Kanagawa, Japan

Taro Fujii