Intel Corporation

Netlogic Microsystems, Inc

Tarjinder Singh

Gopalakrishnan Perur Krishnan

Srajudheen Makkadayil

Rekha Manjunath

Eswar Vadlamani

Saurabh Patil

Vikram Sharma Mailthody

Ramesha Doddamane

An integrated circuit that is capable of performing sequence alignment via dynamic programming methods is provided. The integrated circuit may include a linear systolic array having series-connected processing engines, each of which has a n-stage deep pipeline. The systolic array may align first and second sequences, wherein the first sequence is divided into multiple segments equal to the internal depth of the pipeline. The systolic array may compute matrix scores for these segments in parallel until the entire sequence matrix score is computed. The internal pipeline structure and a loopback memory within the systolic array are configured to take care of any required data dependencies in the computation of the matrix scores.

Systolic array of pipelined processing engines for implementing dynamic programming algorithms

A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator () that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (). An address range selector circuit () can limit the range of addresses generated by an address generator (). Once defective addresses for a first range have been detected, an address range selector circuit () can test another range. An entire address range can thus be tested regardless of the depth of a fault address store ().

Programmable address space built-in self test (BIST) device and method for fault detection

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Bengaluru, India

Tarjinder Singh