Novellus Systems Incorporated

Lam Research Corporation

Tariq Majid

Shantinath Ghongadi

Kousik Ganesan

Bryan L Buckalew

Robert Rash

Seshasayee Varadarajan

Jeff Hawkins

Zhian He

Steven T Mayer

Jonathan David Reid

Aaron LaBrie

Brian Evans

Eric G Webb

Sesha Varadarajan

John H Sukamto

Quan Ma

Yuichi Takada

Bryan Pennington

Ludan Huang

Margolita M Pollack

Doyeon Kim

Shanthinath Ghongadi

Various embodiments herein relate to methods and apparatus for electroplating metal on a substrate. In many cases, an electroplating process may be monitored to ensure that it is operating within a pre-defined processing window. This monitoring may involve application of a controlled potential between the substrate and a reference electrode after the electroplating process is substantially complete (e.g., after recessed features on the substrate are substantially filled). The current delivered to the substrate during application of the controlled potential is monitored, and a peak current is determined. This peak current, often referred to herein as the potential-controlled exit peak current, can be compared against an expected range to determine whether the electroplating process is operating as desired.

Gap fill process stability monitoring of an electroplating process using a potential-controlled exit step

Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.

Apparatus and method for edge bevel removal of copper from silicon wafers

Certain embodiments disclosed herein pertain to methods and apparatus for electrodepositing material on a substrate. More particularly, a novel membrane for separating the anode from the cathode/substrate, and a method of using such a membrane are presented. The membrane includes at least an ion exchange layer and a charge separation layer. The disclosed embodiments are beneficial for maintaining relatively constant concentrations of species in the electrolyte over time, especially during idle (i.e., non-electroplating) times.

Membrane design for reducing defects in electroplating systems

Embodiments of a closed-contact electroplating cup assembly that may be rapidly cleaned while an electroplating system is on-line are disclosed. One disclosed embodiment comprises a cup assembly and a cone assembly, wherein the cup assembly comprises a cup bottom comprising an opening, a seal surrounding the opening, an electrical contact structure comprising a plurality of electrical contacts disposed around the opening, and an interior cup side that is tapered inwardly in along an axial direction of the cup from a cup top toward the cup bottom.

Rapidly cleanable electroplating cup seal

Embodiments of a closed-contact electroplating cup are disclosed. One embodiment comprises a cup bottom comprising an opening, and a seal disposed on the cup bottom around the opening. The seal comprises a wafer-contacting peak located substantially at an inner edge of the seal. The embodiment also comprises an electrical contact structure disposed over a portion of the seal, wherein the electrical contact structure comprises an outer ring and a plurality of contacts extending inwardly from the outer ring, and wherein each contact has a generally flat wafer-contacting surface. The embodiment further comprises a wafer-centering mechanism configured to center a wafer in the cup.

Electroplating cup assembly

Closed contact electroplating cup assembly

Rapidly cleanable electroplating cup assembly

A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.

Electroplating using DC current interruption and variable rotation rate

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Wilsonville, OR, United States of America

Tariq Majid