Nxp B.v.

Tarik Saric

Juan Felipe Osorio Tamayo

Nenad Pavlovic

Vladislav Dyachenko

Erwin Johannes Gerardus Janssen

Zhirui Zong

Salvatore Drago

Manoj Kumar Patasani

Piotr Gibas

Systems and methods for testing electrical connections between a chip and external circuitry are discussed. In some embodiments, a chip may include an Input/Output (I/O) terminal and a test circuit coupled to the I/O terminal, wherein an oscillating frequency of the test circuit changes in response to an impedance change at the I/O terminal due to a connection failure or degradation.

Systems and methods for testing electrical connections between a chip and external circuitry

Aspects of the present disclosure are directed to injection locking and related apparatuses. As may be implemented in accordance with one or more embodiments, an apparatus includes a plurality of injection-locking circuits configured to receive an injection signal, each injection-locking circuit including a mixer and a lock-detection circuit. In each of the injection-locking circuits, the lock-detection circuit detects a lock-status relationship between the injection signal and a signal output from the injection-locking circuit. In response to the lock-status relationship indicating an unlocked condition, a phase/magnitude of the injection signal is adjusted. In response to the lock-status relationship indicating a locked condition, transmission of an FM continuous wave (FMCW) chirp signal is facilitated.

Phase-adjustable injection-locking

Exemplary aspects of the present disclosure involve a system and related method of PLL circuitry in a chirp signaling FMCW system having a variable PLL bandwidth (BW). To adjust the BW, the PLL circuitry may provide for variable capacitance in the circuitry. This capacitance change may allow for a bandwidth for one slope, as used for the acquisition period. The capacitance may then be adjusted to allow for a different bandwidth for another slope which is used to reset the circuitry in preparation for another frequency sweep. Adjusting the PLL BW, via variable capacitance, may be used to mitigate phase noise which can adversely the PLL.

Bandwidth adjustability in an FMCW PLL system

Embodiments are directed to apparatuses and methods involving a phase-error tracking circuit. An example apparatus includes a divide-by phase locked loop (PLL) circuit to generate a continuous wave signal that sweeps over a frequency range in response to a divider feedback signal and to a reference signal. The apparatus further includes the phase-error tracking circuit defining a phase-error window in which the divide-by PLL circuit is to lock based on a slope associated with a rate of change of the frequency range, and indicating whether a phase error between the divider feedback signal and the reference signal coincides with the phase-error window.

Apparatuses and methods involving phase-error tracking circuits

A chirp-generator comprising a phase-detector for providing a phase-difference-signal representative of a phase difference between a clock-input-signal and a feedback-signal. A VCO-circuit is configured to provide a chirp-generator-output-signal based on the phase-difference-signal. The VCO-circuit comprises a switched-varactor-bank, which includes a plurality of varactors, and a varactor-switch associated with each of the plurality of varactors. The varactor-switch is configured to selectively control whether or not the associated varactor contributes to the capacitance of the VCO-circuit, based on the state of a varactor-control-signal. The chirp-generator also includes a feedback-component configured to: receive the chirp-generator-output-signal; and apply a variable-multiplication-factor to the chirp-generator-output-signal in order to provide the feedback signal for the phase-detector. A controller provides a sequence of different variable-multiplication-factors to the feedback-component; and provides varactor-control-signals to the plurality of varactors such that the varactors are sequentially controlled such that they contribute to the capacitance of the VCO-circuit.

Chirp generator

A phase locked loop for generating a frequency chirp is disclosed. The phase locked loop comprises a phase frequency detector configured to receive a reference frequency signal at a first input, a low pass filter configured to receive a current from the phase frequency detector at a filter input, and to output a control voltage, a voltage controlled oscillator configured to generate the frequency chirp at an output in response to receiving the control voltage, a feedback path connecting the output of the voltage controlled oscillator to a second input of the phase frequency detector, the feedback path comprising a frequency divider; and a timing module configured to generate a reset pulse. The low pass filter comprises a plurality of capacitors connected in parallel between the filter input and a common voltage line; and a voltage source configured to generate an initial control voltage. The voltage source is switchably connected to a node between a first capacitor of the plurality of capacitors and the common voltage line, and is connected to the node during a chirp reset mode defined by the reset pulse such that the voltage at the node is substantially equalized to the initial control voltage.

Phase locked loop

A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.

Time to digital converter and phase locked loop

A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input. The phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.

The invention relates to frequency synthesizer circuits, and in particular to frequency synthesizer circuits characterized by a small channel spacing. Embodiments disclosed include a frequency synthesizer circuit for a radio receiver, the circuit comprising: a digitally controlled oscillator configured to generate an output signal with an output frequency on application of an oscillator enable signal; a delay module; configured to delay an input reference signal to generate a delayed reference signal; and a duty cycle module configured to modulate the oscillator enable signal based on a period of an input reference signal and the delay of the delayed reference signal, such that a ratio between the output frequency and the frequency of the input reference signal is a non-integer.

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Eindhoven, Netherlands

Tarik Saric