International Business Machines Corporation

Tari S Gordon

Thomas B Chadwick, Jr

Rahul K Nadkarni

Eric Jasinski

Michael Richard Quellette

A method and structure for improving a content addressable memory array has a plurality of serially connected memory sub-arrays (which include at least one memory cell), a matchline connected to each of the sub-arrays, a valid memory cell, a comparator receiving input from the matchline and valid memory cell, a sinkline output from the comparator, and a precharge device. The sinkline and matchline are reset from a first voltage to a second voltage depending upon the results of a compare operation of the input data to the data in the storage device. When the second voltage appears on the matchline and the first voltage appears on the sinkline this indicates a match between the data within all of the sub-arrays and the input data.

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Burlington, VT, United States of America

Tari S Gordon