Xilinx, Inc.

Tarek Eldin

Feng Wang

David M Mahoney

Himanshu J Verma

Zhi-min Ling

Eric Thorne

A method for determining propagation delay differences for conductive lines of an integrated circuit is described. A first path is formed by coupling a first portion of conductive lines together. The first portion is associated with a first region of the integrated circuit. The first path is coupled in a ring oscillator, and a first delay is determined. A second path is formed by coupling a second portion of the conductive lines together. The second portion is the first portion except for at least a first conductive line in the first portion of the conductive lines being swapped for a second conductive line. The second conductive line is associated with a second region of the integrated circuit. The second path is coupled in the ring oscillator circuit. A second delay is determined, and an incremental difference between the first delay and the second delay may be determined.

Method for determining interconnect line performance within an integrated circuit

The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point ('PIP') in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

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San Jose, CA, United States of America

Tarek Eldin