Intel Corporation

Intel Ndtm US LLC

Sk Hynix Nand Product Solutions Corp.

Tarek Ahmed Ameen Beshari

Shantanu R Rajwade

Narayanan Ramanan

Matin Amani

Ali Khakifirooz

Xiang Yang

Sagar Upadhyay

Arun Thathachary

Pranav Kalavade

Pranav Chava

Ahsanur Rahman

Pratyush Chandrapati

A storage device charges bitlines in preparation for a program pulse. To charge the bitlines, the storage device connects the bitlines to an external regulator instead of an internal regulator to prepare them for the program pulse. The system can charge all bitlines to the external regulator high voltage reference before changing to the internal regulator for bitline stabilization before the program pulse.

Efficient bitline stabilization for program inhibit in NAND arrays

Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.

Simultaneous programming of multiple sub-blocks in NAND memory structures

An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.

Program verify process having placement aware pre-program verify (PPV) bucket size modulation

For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.

Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit

Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.

Using variable voltages to discharge electrons from a memory array during verify recovery operations

Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array.

Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell

An apparatus is described. The apparatus includes a storage device controller having logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells. The second threshold level is higher than the first threshold level.

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Santa Clara, CA, United States of America

Tarek Ahmed Ameen Beshari