Freescale Semiconductor,inc.

Taras A Kirichenko

Brian A Winstead

Konstantin V Loiko

Sung-Taeg Kang

Ramachandran Muralidhar

Cheong Min Hong

Ko-Min Chang

Rajesh A Rao

Jane A Yater

A method of making a semiconductor device on a semiconductor layer includes: forming a gate dielectric over the semiconductor layer; forming a layer of gate material over the gate dielectric; etching the layer of gate material to form a select gate; forming a storage layer that extends over the select gate and over a portion of the semiconductor layer; depositing an amorphous silicon layer over the storage layer; etching the amorphous silicon layer to form a control gate; and annealing the semiconductor device to crystallize the amorphous silicon layer.

Method for making a stressed non-volatile memory device

A method of making a semiconductor device on a semiconductor layer includes forming a gate dielectric and a first layer of gate material over the gate dielectric. The first layer is etched to remove a portion of the first layer of gate material over a first portion of the semiconductor layer and to leave a select gate portion. A storage layer is formed over the select gate portion and over the first portion of the semiconductor layer. A second layer of gate material is formed over the storage layer. The second layer of gate material is etched to remove a first portion of the second layer of gate material over a first portion of the select gate portion. A portion of the first portion of the select gate is etched out to leave an L-shaped select structure. The result is a memory cell with an L-shaped select gate.

Stressed semiconductor device and method for making

A semiconductor process and apparatus are disclosed for forming a split-gate thin film storage NVM device () by forming a select gate structure () on a first dielectric layer () over a substrate (); forming a control gate structure () on a second dielectric layer () having embedded nanocrystals () so that the control gate () is adjacent to the select gate structure () but separated therefrom by a gap (); forming a floating doped region () in the substrate () below the gap () formed between the select gate structure and control gate structure; and forming source/drain regions () in the substrate to define a channel region that includes the floating doped region ().

Split-gate thin film storage NVM cell with reduced load-up/trap-up effects

Growing community of inventors

Austin, TX, United States of America

Taras A Kirichenko