Cadence Design Systems, Inc.

Taranjit Singh Kukal

Steven Roberts Durrill

Arnold Ginetti

Vikas Kohli

Nikhil Gupta

Vikrant Khanna

Arnold Jean Marie Gustave Ginetti

Balvinder Singh

Jilin Tan

Xuegang Zeng

Kenneth Robert Willis

Dennis Nagle

Ambrish Kant Varma

Kumar Chidhambara Keshavan

Feras Al-Hawari

Bradford Griffin

Raymond Komow

Rameet Pal

Amit Kumar Sharma

Hui Qi

Madhur Sharma

Utpal Bhattacharyya

Steve Durrill

Alok Tripathi

Dingru Xiao

Jasleen Kaur Ahuja

Kunal Gupta

Surender Singh

Vikas Aggarwal

Ritabrata Bhattacharya

An-Yu Kuo

Rohit Shukla

Frank X Farmar

Amit Chopra

Abhay K Agarwal

Tyler James Lockman

Shivani Sharma

Siddharth Mohan

Rajesh Prasad Singh

Preeti Chauhan

Abhishek Dabral

Bradley Brim

Avinash Singh

Raja Vitra

Heiko Dudek

Jerry Alan Long

Chris Banton

Jitin Jacob

Chris Cheung

Charu Kapoor

Keith Felton

Navkamal Rakra

Sankaran Dharmarajan

Jagdish Lohani

Harmohan Singh

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a printed circuit board schematic and one or more electronic circuits. Embodiments may further include automatically generating, one or more circuit templates based upon, at least in part, the printed circuit board schematic and one or more electronic circuits. The one or more circuit templates may be stored at an electronic design database. Embodiments may also include receiving a current printed circuit board schematic and automatically determining whether a subcircuit of the current printed circuit board schematic is an exact or approximate match with the one or more circuit templates.

System and method for performance estimation for electronic designs using subcircuit matching and data-reuse

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, using at least one processor, an electronic design schematic and splitting, using the at least one processor, the electronic design schematic into a plurality of subcircuits. Embodiments may further include independently simulating each of the plurality of subcircuits to generate simulation results and analyzing the simulation results to determine over-stress associated with the plurality of subcircuits.

System and method for computing electrical over-stress of devices associated with an electronic design

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include providing, using at least one processor, an electronic circuit design including an integrated circuit ('IC') or package schematic and generating a power distribution network ('PDN') based upon at least in part, the electronic circuit design including the IC or package. The method may further include obtaining a PDN model having one or more port mappings between one or more layout terminals and one or more schematic pin-names and stitching the PDN model and the IC or package schematic into a combined PDN and IC or package schematic model. The method may also include simulating the combined PDN and IC or package schematic model using the at least one processor.

System and method for power-grid aware simulation of an IC-package schematic

Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations. Some other methods and systems are directed at performing channel analyses for a communication interface of an electronic system by concurrently applying stimuli to corresponding transmitters of a communication interface, characterizing the communication interface to perform a single simulation on the communication interface with the stimulus to determine responses at receivers of the communication interface, and determining waveform responses of the communication interface by performing operations on the responses and an input signal to the communication interface.

Method, system, and computer program product for performing channel analyses for an electronic circuit design including a parallel interface

Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view

Embodiments included herein are directed towards a system and method for implementing an IC package design with an IC package design estimator. Embodiments may include estimating a number of layers for an integrated circuit (IC) package design that includes a plurality of IC die designs. Embodiments may further include determining whether the estimated number of layers can accommodate routing demands for interconnections between the IC package design and each of the plurality of IC die designs. Embodiments may also include identifying a number of layers required to perform routing between each of the plurality of IC die designs. Embodiments may further include determining a power layer or ground layer based upon, at least in part, one or more factors and generating an output for the IC package design based upon, at least in part, the estimated number of layers and the power layer or ground layer.

System and method to estimate a number of layers needed for routing a multi-die package

Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design

Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected portion of the netlist. Embodiments may also include performing one or more operations associated with the schematic symbol and translating the one or more operations into simulation commands.

System and method for schematic-driven generation of input/output models

Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be generated or identified for the electronic design at least by using a transmission line model based in part or in whole upon connectivity information or a hierarchical structure of the electronic design. The electronic design may then be modified or updated based in part or in whole upon results of performing one or more analyses on the extracted view with the transmission line model.

Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design

Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic ('EM') model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.

System and method to generate schematics from layout-fabrics with a common cross-fabric model

A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell

Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic design

The present disclosure relates to a system and method for simulating channels in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design including at least one channel. Embodiments may further include transmitting two or more inputs from two or more transmitter drivers on two or more wires to the at least one channel. In some embodiments, the inputs may be distributed across the wires based upon a chordal code. Embodiments may also include generating simulated waveforms based upon the inputs. Embodiments may further include transmitting the simulated waveforms from the channel on the wires to a comparator block. Embodiments may also include comparing the simulated waveforms on the wires at the comparator block to produce two or more simulated outputs. Embodiments may include transmitting the simulated outputs from the comparator block on the wires to two or more post-comparator receivers.

System and method for simulating channels

Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.

Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awareness

Disclosed are techniques for generating a parasitic-aware simulation schematic across multiple design fabrics. These techniques identify a first extracted model from existing extracted models for a first circuit component design in a first layout in a first design fabric of an electronic design that spans across multiple design fabrics. These techniques further generate a simulation schematic by inserting the first extracted model into the simulation schematic. In addition, a simulation may be performed with the simulation schematic to generate simulation results. Schematic models, if existing, may also be used to revise the simulation schematic. For circuit component designs corresponding to no extract models or schematic models, one or more extracted models placeable in the simulation schematic may also be constructed to update the simulation schematic.

Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabrics

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Delhi, India

Taranjit Singh Kukal