International Business Machines Corporation

Taqi Nasser Buti

Louis L Hsu

Seiki Ogura

Joseph F Shepard

Klaus D Beyer

Chang-Ming Hsieh

Rajiv V Joshi

Jente Benedict Kuang

Robert C Wong

Peter Juergen Klim

Hyun J Shin

Mary Joseph Saccamango

Somnuk Ratanaphanyarat

Dung Q Nguyen

Hung Qui Le

Christopher McCall Durham

Brian William Curran

Maureen Anne Delaney

Robert Greg McDonald

Saiful Islam

Jafar Nahidi

Matthew J Amatangelo

Ronald N Schulz

Mark E Jost

Zakaria Mahmood Khwaja

An instruction buffer and a method of buffering instructions. The instruction buffer including: a memory array partitioned into multiple identical memory sub-arrays arranged in sequential order from a first memory sub-array to a last memory sub-array, each memory sub-array having multiple instruction entry positions and adapted to store a different instruction of a set of concurrent instructions in a single instruction entry position of any one of the memory sub-arrays, the set of concurrent instructions arranged in sequential order from a first instruction to a last instruction

Method and circuit for reading and writing an instruction buffer

According to one form of the invention, an apparatus includes first timing circuitry, at least one stage of logic circuitry and second timing circuitry. The first timing circuitry has a first data input and a latch with a latch data input coupled to the first data input and a latch data output coupled to an input of the least one stage of logic circuitry. The second timing circuitry has a latch and an edge detector with respective latch and edge detector data inputs coupled to a data output of the at least one stage of logic circuitry. The edge detector has an output coupled to a control input of the second timing circuitry latch for triggering capture of an output data signal on the data output of the at least one stage of logic circuitry responsive to detecting a signal transition.

Multistage, single-rail logic circuitry and method therefore

A non-conventional CAM (content addressable memory) and register mapper organization and circuit implementation is provided which allows simultaneous execution of a large number of CAM searches. All compare circuits are placed outside of the CAM in separate match arrays where the actual comparisons occur. The CAM cell contains only latches to hold the CAM stored bit of data and a multi-port MUX to update the CAM content. The CAM bits are driven to the match arrays for match generation. The structure of the CAM and search engine facilitates implementation of the register mapper as a group of custom arrays. Each array is dedicated to execute a specific function. All of the arrays are aligned and each row of an array is devoted to one register to keep current state, shadow state and controls for that register. In an exemplary embodiment, eight custom arrays are used to execute various functions of the register mapper.

Content addressable storage apparatus and register mapper architecture

The method and system provided may be utilized to efficiently perform register mapping in a superscalar processor, wherein a content addressable memory array stores mapping data which indicates the relationship between logical registers and physical registers and wherein compare circuitry compares the mapping data with a logical register identifier to provide the related physical register. The content addressable memory is updated with new mapping data while concurrently driving the new mapping data along a bus to compare circuitry. The new mapping data is compared with a logical register identifier in the compare circuitry, such that for instruction dispatch cycles which require updating and reading the content addressable memory, the new mapping data is dynamically written through to the compare circuitry during the update of the content addressable memory.

Method and system for super-fast updating and reading of content addressable memory with a bypass circuit

SOI Transistor Having a Self-aligned Body Contact An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

SOI transistor having a self-aligned body contact

An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor. The flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. Other embodiments of the apparatus of the present invention are described herein.

Ramp-up rate control circuit for flash memory charge pump

A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.

Discharge circuit in a semiconductor memory

An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

An improved storage system for use with computers. The system includes a memory array bifurcated into a first and second array segment and a differential sense amplifier configured for selective operation in a first mode establishing one array segment as a reference load and the other array segment as a dynamic load, and a second mode establishing the other array segment as a reference load and the one array segment as a dynamic load. The amplifier senses changes in a parameter in the dynamic load with respect to the reference load.

Storage system

An improved differential sense amplifier for sensing differences in a parameter at a first locus coupled with a first signal source and a second locus coupled with a second signal source. The sensing is effected by a first sensing element coupled with the first locus and a second sensing element coupled with the second locus. The improvement comprises the first sensing element and the second sensing element having differing sensitivities. In the preferred embodiment of the invention, the sensing elements are field effect transistors, and the sensitivity is established by a threshold voltage characteristic. Preferably, the first signal source provides a dynamic signal to be measured and the second signal source provides a reference signal against which the dynamic signal's changes are compared.

Differential sense amplifier

Method of forming a SOI transistor having a self-aligned body contact

A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

Semiconductor device and wafer structure having a planar buried

A method of thinning SOI films for providing ultra-thin active device regions having excellent thickness uniformity and further having self-aligned isolation regions between the active device regions is disclosed. A substrate having an isolation layer formed thereon and further having a single crystal silicon layer formed upon the isolation layer is first provided. A thermal oxide layer is grown upon the silicon layer, patterned in desired regions corresponding to polish stop regions positioned between predetermined active device regions, and etched. The silicon layer is thereafter etched according to the patterned thermal oxide layer with a high selectivity etch, thereby creating grooves in the silicon layer. An insulative polish stop material is then deposited upon the thermal oxide, silicon, and isolation layers, the polish stop material forming top, sidewall, and bottom polish stop material thereon, respectively, partially filling the grooves, and further wherein the bottom polish stop material comprises a prescribed thickness. Polysilicon is deposited upon the polish stop material to further completely fill the grooves and then is planarized down to the top polish stop material. The top polish stop material and the oxide layer are then etched away. Lastly, by chemical-mechanical polishing, the silicon, sidewall polish stop material, and polysilicon are thinned down to the bottom polish stop material, whereby active device regions have uniform thickness corresponding to the thickness of the bottom polish stop material.

Method for thinning SOI films having improved thickness uniformity

A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1,000 .ANG. and bipolar devices formed in a thick epitaxial layer of 1 .mu.m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide-bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1,000 .ANG. over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 .mu.m in the bipolar regions and a 1,000 .ANG. thick layer of epitaxial silicon in the CMOS regions.

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Millbrook, NY, United States of America

Taqi Nasser Buti