U-nav Microelectronics Corporation

Atheros Technology Ltd.

Tapani Ritoniemi

Ville Eerola

A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N&#x2267;2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

Matched filter and spread spectrum receiver

The present invention relates to a device for generating at least one code phase (Ce, Cp, Ci) the device comprising a shift register () comprising N outputs and to which a code sequence (Cin) to be phased is applied, and at least one logic branch () controlled by at least one combination control signal on the basis of which the logic branch combines the code phase from i outputs of the shift register (). N is an integer greater than 2 and i is an integer between 2 and N. Said at least one logic branch preferably comprises i two-input selectors (tototo), to the first input of each of which is connected one input of the shift register () and to the second input is connected one combination control signal (ecto ec, pcto pc, lcto lc), and an i-input combiner (), to whose outputs are connected the outputs of said i selectors and from whose output said code phase is obtained.

Correlator

A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N2. The matched filter also stores K reference signals, wherein K2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

A device for detecting a demodulated signal received by a spread spectrum receiver and converted into digital samples. The device is characterized by a matched filter for calculating the correlation between an incoming signal and at least one reference signal, an oscillator for generating a sampling frequency, and a sampling circuit for re-sampling the demodulated digital sample signal at the sampling frequency, which is such that the timing of samples of the references signals of the matched filter corresponds to the timing of a sample signal going from the sampling circuit to the matched filter. The device also includes a multiplier in which the sample signal is multiplied by a carrier replica generated locally before the sampling circuit or thereafter, to remove the carrier from the sample signal.

Signal acquisition system for spread spectrum receiver

The invention relates to a digital receiver part of a spread spectrum receiver, to which receiver part an intermediate-frequency signal (S) is applied, and from whose output a carrier and code demodulated signal (S) is obtained, comprising a code mixer () for code demodulation of the signal by means of a local spreading code replica, a carrier mixer () for carrier demodulation of the signal by means of a local carrier replica, and first decimation means (). The receiver part of the invention is characterized in that said code mixer () is arranged to precede said carrier mixer () on the signal path, said first decimation means () are arranged between said code mixer () and said carrier mixer (), and the output of the carrier mixer () is functionally connected as an output (S) of the digital receiver part.

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Peräseinäjoki, Finland

Tapani Ritoniemi