International Business Machines Corporation

Tapan K Nayak

Dharmendra S Modha

Pallab Datta

John Vernon Arthur

Myron Dale Flickner

Andrew S Cassidy

Jun Sawada

Arnon Amir

Steven Kyle Esser

Rathinakumar Appuswamy

Filipp A Akopyan

Carlos O Otero

Alexander Andreopoulos

Brian Taba

Michael Vincent DeBole

Brian Seisho Taba

Filipp Akopyan

Carlos Ortega Otero

Andrew Stephen Cassidy

Conflict-free, stall-free, broadcast networks on neural inference chips are provided. In various embodiments, a neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node.

Conflict-free, stall-free, broadcast network on chip

Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

Neural network weight distribution from a grid of memory elements

Hardware optimization of neural networks is provided. In various embodiments, an output-induced receptive field of each of a plurality of layers of a neural network is determined. From each of the plurality of layers any portions of their respective input that falls outside their respective output-induced receptive field are trimmed. For each of the plurality of layers, a plurality of mappings of the layer to physical neurosynaptic cores are determined. A mapping is determined having a minimum total number of cores required for the neural network based on the plurality of mappings.

Optimized partitioning of multi-layer networks in core-based neurosynaptic architectures

Neural inference chips for computing neural activations are provided. In various embodiments, the neural inference chip is adapted to: receive an input activation tensor comprising a plurality of input activations; receive a weight tensor comprising a plurality of weights; Booth recode each of the plurality of weights into a plurality of Booth-coded weights, each Booth coded value having an order; multiply the input activation tensor by the Booth coded weights, yielding a plurality of results for each input activation, each of the plurality of results corresponding to the orders of the Booth-coded weights; for each order of the Booth-coded weights, sum the corresponding results, yielding a plurality of partial sums, one for each order; and compute a neural activation from a sum of the plurality of partial sums.

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

Hardware placement of neural networks is provided. In various embodiments, a network description is read. The network description describes a spiking neural network. The neural network is trained. An initial placement of the neural network on a plurality of cores is performed. The cores are located on a plurality of chips. Inter-chip communications are measured based on the initial placement. A final placement of the neural network on the plurality of cores is performed based on the inter-chip communications measurements and the initial placement. The final placement reduces inter-chip communication.

Hardware-software co-design of neurosynaptic systems

Graph partitioning and placement for multi-chip neurosynaptic networks. According to various embodiments, a neural network description is read. The neural network description describes a plurality of neurons. The plurality of neurons has a mapping from an input domain of the neural network. The plurality of neurons is labeled based on the mapping from the input domain. The plurality of neurons is grouped into a plurality of groups according to the labeling. Each of the plurality of groups is continuous within the input domain. Each of the plurality of groups is assigned to at least one neurosynaptic core.

Graph partitioning and placement for multi-chip neurosynaptic networks

Detection, tracking and recognition on networks of digital neurosynaptic cores are provided. In various embodiments, an image sensor is configured to provide a time-series of frames. A first artificial neural network is operatively coupled to the image sensor and configured to detect a plurality of objects in the time-series of frames. A second artificial neural network is operatively coupled to the first artificial neural network and configured to classify objects detected by the first neural network and output a location and classification of said classified objects. The first and second artificial neural networks comprise one or more spike-based neurosynaptic cores.

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San Jose, CA, United States of America

Tapan K Nayak