Alcatel-lucent USA Inc.

Lucent Technologies Inc.

Rutgers, the State University of New Jersey

At+t Corp.

At&t Bell Laboratories

Tapan J Chakraborty

Bradford Van Treuren

Chen-Huan Chiang

Suresh Goyal

Michele Portolan

Vishwani D Agrawal

Aditya Jagirdar

Roystein Oliveira

Sudipta Bhawmik

Bradford Gene VanTreuren

Nilanjan Mukherjee

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.

Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing

The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level. In one embodiment, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level. In one embodiment, the second hierarchical level may be used for independent, parallel testing while data continues to be propagated through the first hierarchical level.

Apparatus and method for isolating portions of a scan path of a system-on-chip

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.

Method and apparatus for describing and testing a system-on-chip

The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy-enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.

Apparatus and method for controlling dynamic modification of a scan path

The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.

Method and apparatus for describing parallel access to a system-on-chip

The invention includes a method and apparatus for injecting dynamic faults in a circuit device. The apparatus includes a first register adapted with selection data identifying selected ones of a plurality of outputs of the circuit device and/or selected ones of a plurality of error registers of the circuit device, a second register adapted with dynamic fault data for propagation toward the selected ones of the outputs of the circuit device and/or the selected ones of the error registers of the circuit device, and a controller for applying the selection data to the first register and the dynamic fault data to the second register in a manner for providing a dynamic fault on each of the selected ones of the outputs of the circuit device and/or each of the selected ones of the error registers of the circuit device.

Method and apparatus for injecting transient hardware faults for software testing

A method and apparatus for a structure of a flip-flop that is tolerant to the noise pulses occurring due to the presence of crosstalk faults by sampling the input data multiple times before and after the active clock edge. The final stored value at the flip-flop is determined by the resolution of a counter circuit residing in the flip-flop, which is activated at the change of the sampled input data. This counter based resolution mechanism allows for the detection and filtering of the noise pulse induced at the input of the flip-flop due to a crosstalk fault.

Fault-tolerant architecture of flip-flops for transient pulses and signal delays

A register designed to detect and correct soft errors in real time. A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voting circuit. If the content of any of these latches is corrupted by soft error, it is filtered out through the majority voting circuit and correct data is passed out from the output of the flip flop. In one embodiment, this design operates as a simple scan flip flop or scan-hold flip flop, and is useful for system testability purposes.

Soft error tolerant flip flops

A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating fault injection values.

Fault injection method and system

A method and system for testing circuit clusters in a boundary scan environment identifies the circuit clusters and corresponding neighboring boundary scan elements, and generates one or more test vectors to be applied to the cluster under test. The generated test vectors are serialized and input into an identified boundary scan element connected to the cluster being tested in the form of a boundary scan test chain. The output of the applied test vectors is observed from an output of another correspondingly identified boundary scan element connected to the cluster under test. During generation of test vectors a list of faults for detecting by each generated vector is maintained such that the observed output can be used to diagnose faults at the component level within the identified cluster.

Method and system for testing cluster circuits in a boundary scan environment

Testing time of interconnections is reducted by splitting up the collection of connection paths to be tested into two or more groups. A set of test vectors, which is applied to each of the groups concurrently, is arranged to insure that the two adjacent connections that are assigned to different groups are not tested concurrently. The user can select the number of groups, and the number of connection paths within each group (which need not be the same for all groups). The disclosed algorithm increases the number of connection paths that are tested with each concatenated test vector, and consequently the number of required test vectors is reduced.

Arrangement for fault detection in circuit interconnections

A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

Bist architecture for detecting path-delay faults in a sequential circuit

Apparatus and method for testing the components and interconnections of a circuit board while the circuit board is, normally, operatively connected in a system. The circuit board contains a plurality of integrated circuits with at least one of the integrated circuits including interface circuitry for interfacing the circuitry on the circuit board to the rest of the system. The circuit board includes testing circuitry for: (a) selectively testing the circuits contained on the circuit board, other than its interface circuits; and (b) selectively testing the interface circuits and their interconnections. The method of the invention includes placing the interface circuitry in a first state for isolating the circuitry on the circuit board from the rest of the system and testing the circuitry on the circuit board, other than the interface circuitry; and placing the interface circuitry in a second state and testing the interface circuitry and its interconnections.

Testing of live circuit boards

High speed testing of a digital circuit may be performed although the rated frequency of the circuit exceeds the frequency capability of the test equipment. A digital circuit may be designed such that a controllable delay may be introduced in the timing paths of the circuit during testing using test stimuli which are applied at a clock rate that is less than the rated frequency of the circuit. By adding delay to the combinational signal path, testing of the circuit for operation at the maximum operating frequency is achieved during testing at a clock rate which is within the capability of the test equipment. The controllable delay may be incorporated as a delay element into a single-clock circuit and controlled by manipulation of the duty-cycle of a clock waveform which is applied to the circuit. The delay circuit is so designed that its function is also testable. In a multi-clock circuit, the delay is added to the circuit by skewing one clock signal with respect to the other clock signals.

Delay testing of high-performance digital components by a slow-speed

Testing of a sequential circuit (10) containing at least one embedded RAM (16) is accomplished by first generating a set of sequential vectors and then applying the vectors in sequence to a set of primary circuit inputs (PO.sub.o -PO.sub.j). The vectors are generated such that upon application to the circuit, the vectors excite potential faults at nodes (A) upstream of the RAM and propagate the effects of the faults through the RAM to the primary circuit outputs (PO.sub.o -PO.sub.j). Also, the test vectors serve to excite faults downstream of the RAM by propagating values through the RAM needed to excite the downstream faults. The fault effects (if any) that propagate to the circuit primary outputs are compared to a set of reference values to determine if any faults are present.

Growing community of inventors

Princeton Junction, NJ, United States of America

Tapan J Chakraborty