Xilinx, Inc.

Csr Technology Inc.

Zoran Corporation

Marvell International Limited

Qualcomm Mems Technologies, Inc.

Credo Technology Group Limited

Microtune (texas), Inc.

Tao Yu

Ping Dong

Chandrasekhar S Thyamagondlu

Jordan C Cookman

Darren S Jue

Ravi S Sunkavalli

Kushagra Sharma

Shuxian Wu

Nicholas Trank

Akhil Krishnan

Chiranjeevi Sirandas

Rogerio Guedes Alves

Sriram Mudulodu

Jungil Park

Saswat Mishra

Hanh Hoang

Tianchen Luo

Tuan Van-Dinh

Junjie Qu

Ramez Nachman

Lei Chen

John West

Don Barnetson

Sanket Shah

An illustrative retimer includes: an upstream interface having an upstream receiver configured to convert a downlink signal into a downlink symbol stream; a downstream interface having a downstream transmitter configured to provide a transmit signal representing the downlink symbol stream; core circuitry having a downstream path and a downstream bypass path; and a controller. The downstream path is configured to convey the downlink symbol stream from the upstream receiver to the downstream transmitter via a receive clock domain component, a core clock domain component, and a transmit clock domain component. The downstream bypass path is configurable to convey the downlink symbol stream from the upstream receiver to the downstream transmitter without any core clock domain components. The controller is configured to disable a clock signal for the transmit clock domain component of the downstream path when the downstream bypass path is enabled.

PCIe retimer with reduced power low latency mode

Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.

Variable buffer size descriptor fetching for a multi-queue direct memory access system

Evicting queues from a memory of a direct memory access system includes monitoring a global eviction timer. From a plurality of descriptor lists stored in a plurality of entries of a cache memory, a set of candidate descriptor lists is determined. The set of candidate descriptor lists includes one or more of the plurality of descriptor lists in a prefetch only state. An eviction event can be detected by detecting a first eviction condition including a state of the global eviction timer and a second eviction condition. In response to detecting the eviction event, a descriptor list from the set of candidate descriptor lists is selected for eviction. The selected descriptor list can be evicted from the cache memory.

Descriptor cache eviction for multi-queue direct memory access

Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.

Descriptor fetching for a multi-queue direct memory access system

A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

Multi-host direct memory access system for integrated circuits

A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.

Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

Customizable multi queue DMA interface

A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.

Interrupt moderation and aggregation circuitry

The present disclosure describes methods and apparatus for implementing a signature-based sleep recovery operation flow for booting a system-on-chip (SoC). When the SoC begins its normal boot flow, a controller retrieves a sleep recovery signature from a register and compares the retrieved sleep recovery signature to a default signature. If the sleep recovery signature matches the default signature, the SoC enters a ROM checksum fail debug flow and, upon satisfying the requirements of the ROM checksum fail debug flow, enters a sleep recovery boot flow, which restores the SoC to the operational state it was in prior to entering the sleep mode. If the sleep recovery signature does not match the default signature, the SoC continues with the normal boot flow or, by use of external pins, can be forced into a normal debug mode flow so that the boot code can be debugged.

Signature-based sleep recovery operation flow

The present invention relates to adaptive beamforming in audio systems. More specifically, aspects of the invention relate to a method for adaptively estimating a target sound signal by establishing a simulation model simulating an audio environment comprising: a plurality of spatially separated microphones, a target sound source, and a number of audio noise sources.

Adaptive microphone beamforming

An adaptive known signal canceller comprising of a known signal canceller filter responsive to a known signal including a known portion of a transmitted signal, the known signal canceller filter operative to generate a filtered known signal, and a subtractor unit responsive to an input signal and operative to generate an output signal, the subtractor unit configured to subtract the filtered known signal from the input signal to generate an output signal, such that the known portion of the transmitted signal is substantially removed from the input signal. The adaptive known signal canceller further comprising of a known signal canceller update unit, responsive to a desired signal and an output signal and operative to continually adjust the coefficients of the known signal canceller filter based on the difference between the output signal and the desired signal, so that the filter coefficients substantially reflect the impulse response of a channel.

Adaptive known signal canceller

Modeling and simulating behavior of a transistor are described. At least one sub-circuit model for modeling at least one second order effect associated with the transistor is obtained. At least one instance parameter for the at least one second order effect is obtained. Operation of a transistor behavior simulator is augmented with the at least one sub-circuit model populated with the at least one instance parameter such that the simulating of the behavior of the transistor produces data that takes into account the at least one second order effect. The at least one second order effect may be an LOD/eSiGe effect, a poly pitch effect, or a DSL boundary effect. Also described is a method for generation of a sub-circuit model.

Modeling second order effects for simulating transistor behavior

A method and apparatus for deinterleaving in a communication system is disclosed. The method and apparatus deinterleave data units using a data deinterleaver; compressed deinterleave input symbol quality information (SQI) units using a compressed deinterleaver, wherein at least one of the input SQI units deinterleaved by the compressed deinterleaver corresponds to at least one of the plurality of data units deinterleaved by the data deinterleaver; and apply the deinterleaved SQI units to the corresponding deinterleaved data units.

Method and apparatus for deinterleaving in a digital communication system

An extended deinterleaver the extended deinterleaver being responsive to at least one input signal, comprised of codewords, and operative to generate a deinterleaved output signal. The extended deinterleaver comprising a storage space organized into B number of appended storage branches, at least one appended storage branch having a storage branch and at least one element N, the received codewords being deinterleaved and buffered by the extended deinterleaver prior to being provided to the variable iteration decoder. Each appended storage branch further having a length that is extended by the length of N, N being at least one element, wherein as a codeword is provided to the variable iteration decoder, other codewords are provided to subsequent appended storage branches, and further wherein each appended storage branch, indexed by 'b', has a length of L+N, wherein Lis the length of the storage branch prior to appending N.

Extended deinterleaver for an iterative decoder

A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a first plurality of parasitic capacitances derived from a plurality of two-dimensional transistor structures (). The first set of coefficients can be inserted into the first expression (). The method further can include determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures (). The second expression can include the first expression (). The method can include inserting the second set of coefficients into the second expression and outputting the second expression ().

Growing community of inventors

Milpitas, CA, United States of America

Tao Yu