Mediatek Corporation

Neuchips Corporation

Gear Radio Electronics Corp.

Tao-Yi Lee

Ming-Da Tsai

Cheng-Chou Hung

Tung-Hsing Lee

Youn-Long Lin

Po-Sen Tseng

Min-Chiao Chen

A fast vector multiplication and accumulation circuit is applied to an artificial neural network accelerator and configured to calculate an inner product of a multiplier vector and a multiplicand vector. A scheduler is configured to arrange a plurality of multiplicands of the multiplicand vector into a plurality of scheduled operands according to a plurality of multipliers of the multiplier vector, respectively. A self-accumulating adder is signally connected to the scheduler and includes a compressor, at least two delay elements and at least one shifter. The compressor is configured to add the scheduled operands to generate a plurality of compressed operands. The at least two delay elements are connected to the compressor. The shifter is configured to shift one of the compressed operands. An adder is signally connected to the output ports of the compressor so as to add the compressed operands to generate the inner product.

Fast vector multiplication and accumulation circuit

A hybrid RF transceiver circuit comprises a first matching network, a second matching network, a first power amplifier, a second power amplifier, and a low noise amplifier. The second matching network is coupled to the first matching network and an antenna. An output port of the first power amplifier is coupled to the first matching network and the second matching network. The output port of the second power amplifier is coupled to the first matching network. The input port of the low noise amplifier is coupled to the second power amplifier and the first matching network. The output port of the low noise amplifier is coupled to a receiver circuit.

Hybrid RF transceiver circuit

A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.

Semiconductor integrated circuit

A hybrid passive device for synergizing at least one passive component which resides in at least one technology is provided. The hybrid passive device includes a first passive component and a second passive component. The first passive component resides in a first technology of the at least one technology and/or a second technology of the at least one technology, the second technology is different from the first technology, and a technology boundary is arranged between the second technology and the first technology. The second passive component of the at least one passive component is different from the first passive component. The second passive component resides in the first technology and/or the second technology, and the first passive component and the second passive component are electromagnetically coupled to each other through the technology boundary.

Growing community of inventors

Taichung, Taiwan

Tao-Yi Lee