Qualcomm Incorporated

Qualcomm Innovation Center, Inc.

Tao Xue

Haw-Jing Lo

Christopher Kong Yee Chun

Rajat Mittal

Ronald Alton

Steven S Thomson

Michael Drop

Ali Iranli

Vinodh Ramesh Cuppu

Moinul H Khan

Hee Jun Park

Mark Bapst

Mehdi Saeidi

Rajit Chandra

Ali Taha

Jeffrey Gemar

Suresh Sugumar

Alex Kuang-Hsuan Tu

Amy Derbyshire

Sachin Dileep Dasnurkar

Mohammad Tamjidi

Thomas Andrew Morison

Juhi Saha

Julien Chaffraix

Su Zhao

Moinul H Kahn

Ronald Frank Alton

Michael J Drop

An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.

Processor power management responsive to a sequence of an instruction stream

A dynamic scheduler is provided that schedules tasks for a plurality of cores based upon current operating characteristics for the cores. The current operating characteristics include a predicted leakage current for each core based upon an analytical model.

Multi-core dynamic workload management using native and dynamic parameters

Aspects include computing devices, systems, and methods for selecting preferred processor core combinations for a state of a computing device. In an aspect, a state of a computing device containing the multi-core processor may be determined. A number of current leakage ratios may be determined by comparing current leakages of the processor cores to current leakages of the other processor cores. The ratios may be compared to boundaries for the state of the computing device in respective inequalities. A processor core associated with a number of boundaries may be selected in response to determining that the respective inequalities are true. The boundaries may be associated with a set of processor cores deemed preferred for an associated state of the computing device. The processor core present in the set of processor cores for each boundary of a true inequality may be the selected processor core.

Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power

Methods and devices for displaying content in a power efficient manner are disclosed. In accordance with many embodiments, content is received that includes a plurality of subcomponents, and a subcomponent with a larger surface is darkened so as to generate at least one darkened subcomponent. In addition, a contrast of selected ones of the subcomponents is adjusted so as to enable the selected ones of the subcomponents to be viewed against the darkened subcomponent while others of the plurality of subcomponents are left in their source format. The at least one darkened subcomponent, selected ones of the subcomponents, and the subcomponents that are in their source format are composited into a composite view; and displayed.

Method and apparatus for content-based reduction of display power

Devices and methods for monitoring one or more central processing units in real time are disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings. A device may include means for monitoring state data associated with the one or more CPUs in real-time, means for filtering the state data, and means for selectively altering one or more system settings at least partially based on filtered state data. A device may also include a sub-sampling circuit configured to receive a hardware core signal from the central processing unit and output a central processing unit state indication, and an infinite impulse response filter connected to the sub-sampling circuit and configured to receive the central processing unit state indication from the sub-sampling circuit.

System and method of monitoring a central processing unit in real time

A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.

Growing community of inventors

San Diego, CA, United States of America

Tao Xue