Apple Inc.

Aeonsemi, Inc.

Tao Mai

Joachim S Hammerschmidt

Robert G Lorenz

Utku Seckin

Simone Gambini

Ky-Anh Tran

Yunteng Huang

This disclosure provides methods, devices, and systems for wireline communications. The present implementations more specifically relate to line driver circuits that support differential and single-ended signaling. In some aspects, a line driver circuit may include a pair of transmit (TX) digital-to-analog converters (DACs) and a 'mock' TX DAC. When operating in a differential mode, the line driver circuit uses both TX DACs to drive a primary data signal and a complementary data signal onto a differential transmission line. When operating in a single-ended mode, the line driver circuit uses only one of the TX DACs to drive the primary data signal onto a single-ended transmission line and converts the complementary data signal to a mock echo signal via the mock TX DAC, where the mock echo signal mimics an echo of the complementary data signal. The mock echo signal may cancel echoes associated with the primary data signal.

Line driver circuit for full-duplex transceivers with support for differential and single-ended signaling

Methods and apparatus for processing signals captured by one or more sensors are disclosed. An example method includes receiving a first signal from a control circuit, the first signal including control data associated with the one or more sensors, recovering a fixed frequency clock signal and a control signal from the first signal, generating a spread spectrum clock signal based on the fixed frequency clock signal, receiving a sensor data signal based at least in part on data captured by the one or more sensors, the spread spectrum clock signal, and the control signal, retiming the sensor data signal based at least in part on the spread spectrum clock signal and the fixed frequency clock signal, and generating an output signal based on the retimed sensor data signal.

Spread spectrum clocking for sensor interface

A digital filter according to the disclosure includes a processing circuit having a memory and a number of parallel processing circuits. The parallel processing circuits perform a convolution operations based on input data and function data that is accessed from the memory. The filter further includes a serializer for serializing data that is received from the processing circuits. A clock generator circuit provides a first clock signal to the processing circuit and a second clock signal to the serializer. The frequency of the second clock signal is greater than that of the first clock signal.

Digital filter with programmable impulse response for direct amplitude modulation at radio frequency

An Nth-order loop filter includes N integrators (where N is an integer value). The loop filter includes an initialization path coupled between an input to the loop filter and an input of at least one of the integrators. A control circuit is coupled to the Nth order filter. During a reset phase, the control circuit causes an initialization voltage to be sampled into a capacitance of the initialization path. During an initialization phase immediately following the reset phase, the control circuit causes the initialization voltage to be conveyed to the input(s) of the at least one integrator.

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Santa Clara, CA, United States of America

Tao Mai