International Business Machines Corporation

Florida International University

St. John's University

Tao Li

Ruilong Xie

Tsung-Sheng Kang

Indira P Seshadri

Ardasheir Rahman

Naphtali David Rishe

Mingjin Zhang

Ekmini Anuja De Silva

Praveen Joseph

Jahkell Lazarre

Weitong Liu

Kangguo Cheng

Alexander Reznicek

Heng Wu

Nelson M Felix

Chih-Chao Yang

Juntao Li

Carl John Radens

Dechao Guo

Su Chen Fan

Larisa Shwartz

Eric R Miller

Genady Grabarnik

Albert M Young

Sung Dae Suk

Liqiao Qin

Wubai Zhou

Nicolas J Loubet

Shogo Mochizuki

Oleg Gluschenkov

Hemanth Jagannathan

Mukta G Farooq

Julien Frougier

Wenyu Xu

Yann Mignot

Kisik Choi

Albert Manhee Chu

Ashim Dutta

Lan Yu

David S Wolpert

Jay William Strane

Wei Wang

Leon Jacob Sigal

Sagarika Mukesh

Eric Miller

Prabudhya Roy Chowdhury

Shravana Kumar Katakam

A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second FETs.

Stacked FETS with contact placeholder structures

A microelectronic device includes a first source and drain structure adjacent to a second source and drain structure. A first conductive contact is in contact with a top surface and side surface of the first source and drain structure. A second conductive contact is in contact with a top surface and side surface of the second source and drain structure. The second conductive contact includes a via extension to connect to a backside component. A separating layer is located between the first conductive contact and the second conductive contact. A first sidewall of the separating layer is flush with the first conductive contact. A second sidewall of the separating layer is flush with the second conductive contact.

Fork sheet device with wrapped source and drain contact to prevent NFET to PFET contact shortage in a tight space

A structure including a plurality of nanosheet transistors each comprising a gate. A gate protrusion extends from the gate towards the backside of one of the plurality of electronic devices. A first dielectric liner is located flush against the sidewalls of the gate protrusion. A contact via connected to a backside surface of the gate protrusion. A second dielectric liner located flush again the sidewalls of the contact via.

Backside gate via structure using self-aligned scheme

An approach for forming semiconductor structure composed of one or more stacked semiconductor devices with a first semiconductor device on a substrate, a first interconnect wiring structure over the first semiconductor device, a second interconnect wiring structure under a second semiconductor device joined to the first interconnect wiring structure, and a third interconnect wiring structure on the second semiconductor device where the first semiconductor device and the second semiconductor device are each one of a memory device or a logic device. The approach includes each of the first interconnect wiring structure, the second interconnect wiring structure, and the third interconnect wiring structure with a contact pitch to the first semiconductor device and to both sides of the second semiconductor device that is less than one hundred nanometers.

Stacked semiconductor devices with topside and backside interconnect wiring

Semiconductor devices and methods of forming the same include forming a first dielectric layer around a semiconductor fin, formed from a first dielectric material, to a target height lower than a height of the semiconductor fin. A second dielectric layer is deposited on the first dielectric layer and is formed from a second dielectric material. A third dielectric layer, formed from the first dielectric material, is formed on the second dielectric layer. The second dielectric layer is etched away to expose a gap on the semiconductor fin. A portion of the semiconductor fin that is exposed in the gap is oxidized to form an isolation layer.

Vertically stacked fin semiconductor devices

A semiconductor channel material structure is provided that has an improved, i.e., increased, effective channel area. The semiconductor channel material structure includes a plurality of semiconductor channel material nanosheets stacked one atop the other. The increased channel area is afforded by providing at least one through-stack semiconductor channel material that extends through at least one of the semiconductor channel material nanosheets.

Gate all-around device with through-stack nanosheet 2D channel

A semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. An input power line is electrically coupled to the backside power delivery network. Dummy transistors are positioned in a circuit with analog or digital circuit elements. A power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. Power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. The device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.

Power gating dummy power transistors for back side power delivery networks

A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.

Transistors with dual power and signal lines

A semiconductor structure comprises two or more vertical fins, a bottom epitaxial layer surrounding a bottom portion of a given one of the two or more vertical fins, a top epitaxial layer surrounding a top portion of the given one of the two or more vertical fins, a shared epitaxial layer surrounding a middle portion of the given one of the two or more vertical fins, and a connecting layer contacting the bottom epitaxial layer and the top epitaxial layer, the connecting layer being disposed to a lateral side of the two or more vertical fins.

Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A metal line is formed on a bottom liner, a sacrificial hardmask on a top surface of the metal line. Portions of the sacrificial hardmask are selectively removed that that do not correspond a desired location of a top via. The remaining sacrificial hardmask is replaced with the top via, the top via and the metal line each tapered such that a width at each respective bottom surface is greater than a width of each respective top surface.

Top via interconnects with line wiggling prevention

A microelectronic structure including a first transistor including a plurality a first channel layers. A second transistor including a plurality of second channel layers, where the first transistor is located adjacent to the second transistors. A dielectric bar located between the first transistor and the second transistor. A first source/drain of the first transistor is located on a first side of the dielectric bar and a second source/drain of the second transistor is located on a second side of the dielectric bar, where the first side is opposite the second side. A first backside contact connected to the first source/drain, where the first backside contact is in contact with first side of the dielectric bar. A second backside contact connected to the second source/drain, where the second backside contact is in contact with the second side of dielectric bar.

Backside CMOS trench epi with close N2P space

Interconnect structures having top vias self-aligned to metal line ends and techniques for formation thereof are provided. In one aspect, an interconnect structure includes: at least one metal line disposed on a substrate; at least one top via over the at least one metal line, wherein the at least one top via is aligned with an end of the at least one metal line, and wherein a sidewall of the at least one top via is curved. A dielectric fill material can be disposed adjacent to the at least one top via having sidewalls that are also curved. A method of fabricating an interconnect structure is also provided.

Self-aligned via to metal line for interconnect

An integrated circuit, a system, and a method to integrate phase change memory and magnetoresistive random access memory within a same integrated circuit in a system. The integrated circuit may include an MRAM and a PCM. The MRAM may include an MRAM bottom electrode, an MRAM stack, and an MRAM top electrode. The PCM may include a PCM bottom electrode, where the PCM bottom electrode has a lower height than the MRAM bottom electrode, a phase change material, and a PCM top electrode.

AI accelerator with MRAM, PCM, and recessed PCM bottom electrode

A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Bottom source/drain etch with fin-cut-last-VTFET

A memory device includes a first field effect transistor (FET) stack on a first bottom source/drain region, which includes a first vertical transport field effect transistor (VTFET) device between a second VTFET device and the first source/drain region, and a second FET stack on a second bottom source/drain region, which includes a third VTFET device between a fourth VTFET device and the bottom source/drain region. The memory device includes a third FET stack on a third bottom source/drain region, which includes a fifth VTFET between a sixth VTFET and the third source/drain region, which is laterally adjacent to the first and second source/drain regions. The memory device includes a first electrical connection interconnecting a gate structure of the third VTFET with a gate structure of the fifth VTFET, and a second electrical connection interconnecting a gate structure of the second VTFET with a gate structure of the sixth VTFET.

Static random access memory using vertical transport field effect transistors

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Albany, NY, United States of America

Tao Li