Globalfoundries Inc.

Intermolecular, Inc.

Tanya Andreeva Atanasova

Mukta G Farooq

Anh Duong

Reiner Willeke

Luke G England

Selaka Bandara Bulumulla

Daniel P Smith

Sukeshwar Kannan

Md Sayed Kaysar Bin Rahim

Daniel Fisher

Greg Nowling

The present disclosure relates to packaging of integrated circuit chips for semiconductor devices. More particularly, the present disclosure relates to packaging of multiple chips for silicon photonics devices. The present disclosure provides a semiconductor device including a photonic integrated circuit (PIC) chip, an inductor positioned over the PIC chip, and a transimpedance amplifier (TIA) chip positioned over the PIC chip. The inductor has a first terminal end and a second terminal end, and the first terminal end is connected to the PIC chip.

Semiconductor devices and methods of forming same

The disclosure is directed to an integrated circuit structure for joining wafers. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material.

Methods of forming integrated circuit structure for joining wafers and resulting structure

One method includes positioning a front side of a first substrate opposite a side of a second substrate, the first substrate comprising an ESD mitigation structure located at an approximate center of the front side, the second substrate comprising at least one TSV structure that extends through the side of the second substrate, the first substrate and the second substrates adapted to be positioned so as to result in the conductive coupling of the at least one TSV structure and the ESD mitigation structure, bending the first substrate to an initial contact position such that an initial engagement between the first substrate and the second substrate will result in conductively coupling between the ESD mitigation structure and the TSV structure, and engaging the first and second substrates with one another such that the ESD mitigation structure and the TSV structure are conductively coupled to one another.

Methods and structures for mitigating ESD during wafer bonding

The disclosure is directed to an integrated circuit structure for joining wafers and methods of forming same. The IC structure may include: a metallic pillar over a substrate, the metallic pillar including an upper surface; a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and a solder material over the upper surface of the metallic pillar, the solder material being within and constrained by the wetting inhibitor layer. The sidewall of the metallic pillar may be free of the solder material. The method may include: forming a metallic pillar over a substrate, the metallic pillar having an upper surface; forming a wetting inhibitor layer about a periphery of the upper surface of the metallic pillar; and forming a solder material over the upper surface of the metallic pillar within and constrained by the wetting inhibitor layer.

Methods for wet etching a UBM layer and the resulting devices are disclosed. Embodiments may include patterning metal bumps on a wafer that has at least two metal layers thereon; exposing the wafer to a first acid solution to remove a portion of a first of the two metal layers exposed by the patterning of the metal bumps; and exposing the wafer to a second acid solution to remove a portion a second of the two metal layers exposed by the patterning of the metal bumps and the exposure of the wafer to the first acid solution, wherein an undercut below the metal bumps, formed by removal of the portions of the first and second metal layers, is less than 1.5 microns.

Etching of under bump mettallization layer and resulting device

Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of HPOin a volume percentage of about 0.07 to about 0.36, HOin a volume percentage of about 0.1 to about 0.7, and a remainder of HO, and optionally NHOH.

Growing community of inventors

Saratoga Springs, NY, United States of America

Tanya Andreeva Atanasova