Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Tang-Jung Chiu

Mill-Jer Wang

Mirng-Ji Lii

Hung-Chih Lin

Chi-Chang Lai

Chia-Heng Tsai

Chen-Hua Douglas Yu

Wen-Chih Chiou

Chi-Hsi Wu

Hsiang-Fan Lee

Shih-Peng Tai

Weii Liao

Hao Chen

Hsin Chia Chen

Jeng Gong

Weil Liao

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and multiple first conductive lines over the semiconductor substrate. The first conductive lines are not electrically connected to each other. The semiconductor device structure also includes multiple first magnetic structures wrapped around portions of the first conductive lines and multiple second conductive lines over the semiconductor substrate. The second conductive lines are electrically connected in series. The semiconductor device structure further includes multiple second magnetic structures wrapped around portions of the second conductive lines. A size of each of the second magnetic structures and a size of each of the first magnetic structures are substantially the same.

Semiconductor device structure with magnetic element

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.

A testing apparatus for testing an integrated circuit package having a plurality of electrical terminals includes a base, a socket, a plurality of conductive pins and a plurality of conductive pillars. The base includes a plurality of electrical contacts. The socket is disposed on the base and includes a bended portion bended away from the base and a plurality of through holes distributed in the socket. The conductive pins are disposed in the through holes respectively and electrically connected to the electrical contacts, wherein each of the conductive pins protrudes from an upper surface of the socket for forming temporary electrical connections with one of the electrical terminals. The conductive pillars are disposed on the base and connected to the bended portion, wherein each of the conductive pillars electrically connects one of the conductive pins and one of the electrical contacts.

Testing apparatus and testing method

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a testing region and multiple first conductive lines over the testing region. The first conductive lines are electrically connected in series. The semiconductor device structure also includes multiple second conductive lines over the testing region. The second conductive lines are electrically connected in series, and the second conductive lines are physically separated from the first conductive lines. The semiconductor device structure further includes multiple magnetic structures wrapping around portions of the first conductive lines and wrapping around portions of the second conductive lines. The magnetic structures are arranged in a column.

Semiconductor device structure with magnetic element in testing region

A semiconductor device is disclosed. The semiconductor device includes: a System on Chip (SoC) die; an integrated passive device (IPD); and a first switch, coupled between the SoC die and the IPD; wherein the IPD and the SoC die are disposed in different wafers and bonded together, and the first switch is controlled to disconnect the IPD from the SoC die when the IPD is under a test; and the first switch is controlled to connect the IPD with the SoC die when the IPD is not under the test. A test system for testing an IPD of a semiconductor device and an associated method are also disclosed.

Semiconductor device, test system and method of the same

A package includes a substrate, the substrate having a first side and a second side, the second side being opposite the first side, and a stack of dies on a first side of the substrate. The package further includes a probing pad on the first side of the substrate, the probing pad being electrically coupled to the stack of dies, and a contact pad on the second side of the substrate, the contact pad being electrically coupled to the stack of dies.

Integrated circuit package with probe pad structure

A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks.

Methods of forming integrated circuit package

A field-effect transistor has an extra gate above a shallow trench isolation (STI) to enhance and to adapt the low-frequency noise induced by an STI-silicon interface. By changing the voltage applied to the STI gate, the field-effect transistor is able to adapt its low-frequency noise over four decades. The field-effect transistor can be fabricated with a standard CMOS logic process without additional masks or process modification.

Growing community of inventors

Hsinchu, Taiwan

Tang-Jung Chiu