Marvell International Limited

Tang Heng

Gregory Burd

Zining Wu

Son Hong Ho

Vincent M Wong

Soichi Isono

A system including a first buffer module, a first encoder module, a control module, and a second buffer module. The first buffer module receives (i) a first block and (ii) a first logical block address (LBA) for the first block from a host, where the first block includes first data. The first encoder module generates a first checksum based on (i) the first data and (ii) the first LBA. The control module generates a second block, where the second block includes (i) the first data, (ii) the first LBA, and (iii) the first checksum. The second buffer module receives a third block from the first buffer module, where the third block includes a second LBA. The second buffer module determines whether the third block is different than the first block depending on whether the second LBA in the third block is different than the first LBA in the second block.

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Tang Heng