Other

Sony Corporation

Sony Electronics Inc

Nvidia Corporation

Sony Electronics Inc., Jointy

Taner E Ozcelik

Shirish C Gadre

Subroto Bose

Moshe Bublil

Gong-san Yu

Yoshinori Shimizu

Pattabiraman Subramanian

Syed Reza

John Hong

Cem I Duru&ouml;z

Gerrit Ary Slavenburg

Takayuki Ishida

Stephen Donald Lew

Thomas Francis Fox

Jen-Hsun Huang

Gong-San Yu

Edward J Paluch

Yew-Koon Tan

Tomonari Tohara

Cem I Duruoz

John C Schafer

Prakash Bare

Chem I Duruoz

Shrish C Gadre

Cem I Duruöz

Cem Duruoz

Sabyasachi Dutta

Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

Digital media processor

A decoder decodes full frame MPEG-2 video by a single method that applies regardless of buffer memory and frame rate conversion considerations. A display control module handles frame rate and field sequence in response to host configuration, trick play command signals, and information in the received bitstream. Pictures are decoded as buffer memory for the decoded pictures becomes available, and picture display attributes are assigned and stored in a table, one string for each decoded picture. Frame rate and field sequence are managed in light of memory constraints, to produce a high quality result without re-decoding data.

Digital video decoding, buffering and frame-rate converting method and apparatus

A variable length decoder (VLD) for decoding MPEG-1 and -2 syntax compliant video bit streams. The VLD includes a micro-sequencer and VLD command decode/execution unit for controlling the MPEG decoding process using a novel instruction set. The instruction set includes a set of commands for decoding the video data and a set of flow control instructions. A rotator/barrel shifter is provided for making a predetermined number of encoded bits from the video bit stream available to the VLD and a variable length table decoder for variable length decoding using the MPEG standard variable length code (VLC) tables. The variable length table decoder shares a prefix pattern matching scheme across all of the VLC tables and organizes the variable length codes into a series of subtables. Each subtable corresponds to one of the unique prefix patterns. Variable length codes are decoded by identifying a leading pattern in the video data bit stream and, in parallel, accessing the subtable corresponding to that leading pattern. Run-length and amplitude level DCT coefficient symbols are stored in compressed form, and decoded as needed by an inverse transform unit. Motion vectors are also stored until needed by a motion compensation unit.

Variable length decoder for decoding digitally encoded video signals

A digital video presentation system is provided with a decoder to decode full frame MPEG-2 video by a single method that applies regardless of buffer memory and frame rate conversion considerations. A display control module handles frame rate and field sequence in response to host configuration, particularly buffer memory size and display type (NTSC or PAL), to host trick play command signals, and to information in the received bitstream. Pictures are decoded as buffer memory for the decoded pictures becomes available, and picture display attributes are assigned and stored in a table, one string for each decoded picture. Field display logic is informed of the to memory address of the next field to be displayed along with the attributes needed for affecting proper field display sequence, and flagging whether the memory is to be freed for use by the decoder as the field is being displayed and whether the decoder is to decode the next picture as the field is being displayed. Where memory is small, opposite field data can be output. Field sequence order is provided for output buffers in the range of from 0.53 to 0.67 frames in size, or a full frame in size. Buffer memory is optimized by maintaining tables of offset variables and accessing a fixed table of memory pointers as fields of data are being displayed. The offset data tables are identified to the display logic, which uses the data in the specified offset table to address rows of memory in which the consecutive rows of particular field to be displayed are stored. The decoder loads offset values into the offset tables as pictures are being decoded and rows of blocks of the picture are stored as memory becomes free.

A single-chip application specific integrated circuit provides autonomous management of playback of digital video and audio. The chip includes a digital video decoder and output system, and a central processing unit controlling said digital video decoder and output system. The central processing unit receives commands to establish a current playback state for management of playback of digital video and audio by said digital video decoder and output system, and responds to a video field synchronization signal and a current playback state, without external instruction, to determine whether to display digital video, whether to decode digital video for display, whether to repeat display of previously decoded digital video, and whether to skip over digital video prior to decoding digital video for output. By delivering commands to the central processing unit, the application specific integrated circuit can be caused to transition between playback states to provide desired playback of said digital video and audio.

Trick playback of digital video data

Display hardware which manages a plurality, e.g. three, potentially overlapping display windows each having its own pixel values and potentially having its own palette, with no limitation as to the position of the windows relative to each other. This capability is provided at a reduced hardware complexity as compared to a parallel hardware approach, by arranging substantial portions of the hardware in a multiplexed fashion so that the same hardware handles the lookup of palette entries for pixel values, regardless of the currently active window. The hardware is arranged so that it may switch in real time from processing data for one window to processing data for another window, whenever the current display coordinate crosses a window boundary.

Display unit architecture

This command manager is an Application Programming Interface (API) which provides a method for receiving and buffering commands from the host so that the host need not wait for the command to be executed, sorting these commands so that time-critical commands are executed appropriately, scheduling nonexclusive commands to the appropriate time, allowing for the prioritization of nonexclusive commands, providing macro command algorithms to allow for simplified interface with the host, providing micro command pass-through to provide an API with flexibility, and provide acknowledgment capability to the host when the command is executed.

Command manager

A method and apparatus for concealing errors during decoding of a video bit stream utilize estimates, if possible, motion vectors in the temporal domain. If estimation in the temporal domain is not possible, motion vectors are estimated in the spatial domain. A macroblock is then estimated based upon the estimated motion vector. If estimation in the spatial domain is not possible, macroblock estimation is made without the use of an estimated motion vector.

Methods and apparatus for error concealment utilizing temporal domain motion vector estimation

A digital video processor and operating method for a receiving raw audio and video data representing images and sound to be played. The processor includes a demultiplexer for receiving the raw audio and video data and providing demultiplexed audio and video data to a memory. A first system time clock provides first time values in response to being continuously clocked by the demultiplexer. A CPU decodes and plays back the audio and video data as a function of the audio and video PTS values. The processor further includes a second system time clock providing second time values in response to being periodically incremented by the CPU. The CPU periodically sets the second system time clock to a second time value equal to a current first time value of the first system time clock in response to a standard play mode, and the CPU periodically sets the first system time clock to a first time value equal to a current second time value of the second system time clock in response to a trick play mode.

Method and apparatus for a virtual system time clock for digital audio/video processor

Methods and apparatus for error concealment while decoding a coded video bit stream

A method and apparatus for changing the number of scan lines in a frame of video data to produce an image represented by the video data that corresponds to a desired aspect ratio. The apparatus includes a pair of finite impulse response filters for processing the decoded chrominance and luminance pixel values stored in memory. The filters permit a plurality of scan lines of chrominance and luminance data to be read and filtered on a continuous basis with any scan line of data being read only once. Thus, the filters provide a very efficient method of providing a frame of a number of output scan lines of chrominance and luminance pixel values that are different from the number of scan lines of chrominance and luminance pixel values in a frame of video data stored in memory.

Letterbox filter apparatus and method

A digital video presentation system is provided with hardware and software logic for mapping the picture data into buffer memory in a way that permits both the reading of motion vector compensated macroblocks of data and the reading of horizontal picture wide scan lines with a low number of memory page crossings. Preferably, the memory is a plurality of rows, for example 16 rows, wide. Preferably, 16 lines of 8-pixel (two 32 pixel wide column) line segments of 8&times;8 pixel blocks are stored in consecutive storage locations followed by the consecutive storage vertically adjacent line segments until one line segment is stored in each logical row of the memory. Then the next horizontally adjacent set of line segments of similarly stored until the right boundary of the picture is reached, then the each additional row of 16 lines of the picture similarly are stored until the bottom of the picture is reached. Each 16&times;16 pixel macroblock of data is stored on a single page; preferably, two horizontally adjacent macroblocks are stored on one page of memory. Each line of the picture is stored in contiguous locations on the same row of the memory. The motion compensation logic interprets motion vectors from the incoming data and calculates addresses for a macroblock of picture data by separating read commands into separate commands where a page boundary divides the macroblock into vertically adjacent rectangles. Memory controller logic further divides such rectangles where they cross boundaries between horizontally adjacent pages of the memory. One fixed address increment of 8 hex steps from line segment to vertically adjacent line segment while another fixed address increment of 80 hex steps horizontally from one 8 pixel line segment to the next, such as across a scan line of the picture.

Motion compensated digital video decoding and buffer memory addressing therefor

Methods and apparatus for error concealment

A decoder system is provided for decoding an input video signal. A buffer memory hold slices of reconstructed B-pictures for display. The decoder is controlled in accordance with an amount of available memory in the buffer (the amount of available memory in the buffer depends both on how much data has been decoded and also upon how much data has been displayed). In addition, a buffer memory input controller controls into which locations of the buffer memory the slices of the reconstructed B-pictures are stored. As a result, only 2.53 frames of buffer memory are required.

Growing community of inventors

Palo Alto, CA, United States of America

Taner E Ozcelik