Kepler Computing Inc.

Intel Corporation

Tanay Gosavi

Sasikanth Manipatruni

Noriyuki Sato

Amrita Mathuriya

Rajeev Kumar Dokania

Niloy Mukherjee

Ian A Young

Chia-Ching Lin

Somilkumar J Rathi

Debo Olaosebikan

Kaan Oguz

Mauricio Manfrini

Pratyush Pandey

Dmitri E Nikonov

Uygar E Avci

Ashish Verma Penumatcha

Kevin O'Brien

Christopher J Wiegand

Benjamin Buford

Jason Y Wu

Carl H Naylor

Angeline Smith

Chelsey Dorow

Kirby Maxey

Rafael Rios

Tofizur Rahman

James David Clarkson

Shriram Shivaraman

Gary Allen

Raseong Kim

Sudarat Lee

John J Plombon

Mustansir Yunus Mukadam

Ramamoorthy Ramesh

Kevin P O'brien

Seung Hoon Sung

Sou-Chi Chang

Gabriel Antonio Paulius Velarde

Fnu Atiquzzaman

Zeying Ren

Debraj Guhabiswas

Abel Fernandez

Jack T Kavalieros

Matthew V Metz

Biswajeet Guha

Hui Jae Yoo

Nazila Haratipour

Urusa Alaan

Pramod Kolar

Neal Reynolds

Hai Li

James Pellegren

Punyashloka Debashis

Emily Walker

Marko Radosavljevic

Mark L Doczy

Kevin Lai Lin

Charles C Kuo

Christopher J Jezewski

Nafees Kabir

Justin Brockman

Md Tofizur Rahman

Darshak Doshi

I-Cheng Tung

Darrell G Schlom

Owen Y Loh

Patrick Theofanis

Michael Christenson

Aditya Kasukurti

Rohan Patil

Rachel A Steinhardt

Ben Buford

Atm G Sarwar

Megan E Holtz

Erik Unterborn

Ahmad Tavakoli

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Integration process for fabricating embedded memory

A spin orbit logic (SOL) device includes a first electrically conductive layer; a layer comprising a ferroelectric material (FE layer) on the first electrically conductive layer; a second electrically conductive layer on the FE layer; and a spin orbit coupling (SOC) stack including a first layer (SOC1 layer) including a first SOC material, and a second layer (SOC2 layer) including a second SOC material, the SOC1 layer adjacent the FE layer.

Ferroelectrically modulated spin orbit logic device

A memory device, an integrated circuit component including an array of the memory devices, and an integrated device assembly including the integrated circuit component. The memory devices includes a first electrode; a second electrode including an antiferromagnetic (AFM) material; and a memory stack including: a first layer adjacent the second electrode and including a multilayer stack of adjacent layers comprising ferromagnetic materials; a second layer adjacent the first layer; and a third layer adjacent the second layer at one side thereof, and adjacent the first electrode at another side thereof, the second layer between the first layer and the third layer, the third layer including a ferromagnetic material. The memory device may correspond to a magnetic tunnel junction (MTJ) magnetic random access memory bit cell, and the memory stack may correspond to a MTJ device.

Differentially programmable magnetic tunnel junction device and system including same

Magnetoelectric spin-orbit logic (MESO) devices comprise a magnetoelectric switch capacitor coupled to a spin-orbit coupling structure. The logic state of the MESO device is represented by the magnetization orientation of the ferromagnet of the magnetoelectric switch capacitor and the spin-orbit coupling structure converts the magnetization orientation of the ferromagnet to an output current. MESO devices in which all or at least some of the constituent layers of the device are perovskite materials can provide advantages such as improved control over the manufacturing of MESO devices and high quality interfaces between MESO layers due to the lattice matching of perovskite materials.

Perovskite-based magnetoelectric spin-orbit logic devices

Integrating embedded memory with logic interconnects

A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.

Method of forming capacitors through wafer bonding

Method of integrating a capacitor including a non-linear polar material with a transistor through wafer bonding

In one embodiment, a piezo-resistive resonator device includes one or more drive transistors with source and drain regions in a first well and a sense transistor with source and drain regions in a second well of opposite polarity than the first well. The gates of the drive and sense transistor are connected to a first direct current (DC) source. The drain region of the sense transistor is connected to a second DC source, and the source and drain regions of the drive transistor are connected to an alternating current (AC) source.

Piezo-resistive resonator device having drive and sense transistors with wells of opposite doping

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

Gate coupled non-linear polar material based capacitors for memory and logic

A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Method of fabricating memory devices using pocket integration

Described herein is a read and write scheme to improve memory reliability. In at least one embodiment, one or more circuitries are provided to perform logic 0 write operation in a first phase and logic 1 write operation in a second phase for a plurality of bit-cells controlled by a word-line. In at least one embodiment, an individual bit-cell comprises a transistor having a gate terminal coupled to the word-line; and a capacitor including non-linear polar material, wherein the capacitor has a first terminal coupled to a plate-line and a second terminal coupled to the transistor, wherein a source or drain terminal of the transistor is coupled to a bit-line.

Time decoupled write operations for non-linear polar material based memory

A pbit device, in one embodiment, includes a first field-effect transistor (FET) that includes a source region, a drain region, a source electrode on the source region, a drain electrode on the drain region, a channel region between the source and drain regions, a dielectric layer on a surface over the channel region, an electrode layer above the dielectric layer, and a ferroelectric (FE) material layer between the dielectric layer and the electrode layer. The pbit device also includes a second FET comprising a source electrode, a drain electrode, and a gate electrode. The drain electrode of the second FET is connected to the drain electrode of the first FET.

Probabilistic computing devices based on stochastic switching in a ferroelectric field-effect transistor

A transistor includes a channel layer including a transition metal dichalcogenide (TMD) material, an encapsulation layer on a first portion of the channel layer, a gate electrode above the encapsulation layer, a gate dielectric layer between the gate electrode and the encapsulation layer. The transistor further includes a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate structure is between drain contact and the source contact.

Encapsulation for transition metal dichalcogenide nanosheet transistor and methods of fabrication

Methods of fabricating planar capacitors on a shared plate electrode

Capacitor devices with shared electrode and methods of fabrication

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Hillsboro, OR, United States of America

Tanay Gosavi