International Business Machines Corporation

Tan V Chu

Terence M Potter

Christopher Hans Olson

John Stephen Muhich

Charles Roberts Moore

Faraydon O Karim

A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher unit for fetching and dispatching instructions to the processor units. A memory management unit (MMU) is established which includes a translation buffer and translation algorithms for implementing page table and address block type translations of every effective address within the data processing system into real addresses within memory. A translation array, which includes a small number of translation objects for translating effective addresses into real addresses, is then established within the fetcher unit. The translation objects are periodically and selectively varied, utilizing the translation capability of the memory management unit (MMU), in response to a failure to translate an effective address into a real address within the fetcher unit. A translation object within the translation array is preferably replaced each time the fetcher unit fails to translate an effective address into a real address by replacing the least recently utilized (LRU) translation object with a newly determined translation object. In the event of a predicted conditional branch instruction, the utilization status (LRU) is temporarily stored and thereafter utilized to restore the translation array to its previous (LRU) state if the predicted conditional branch is resolved as incorrect. In this manner, the least recently utilized (LRU) state of the translation array will not be corrupted by incorrect path predictions.

Method and system for distributed instruction address translation in a

An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.

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Austin, TX, United States of America

Tan V Chu