Chartered Semiconductor Manufacturing Ltd (corporation)

Tan Juan Boon

Hsia Liang Choo

Alan Cuthbertson

Zhang Bei Chao

Lim Yeow Kheng

Liu Wuping

Zhang Fan

Chok Kho Liep

John Leonard Sudijono

Liu Huang

A structure and method for an improved a bond pad structure. A top wiring layer and a top dielectric (IMD) layer over a semiconductor structure are provided. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. A buffer opening is formed in the buffer dielectric layer exposing at least of portion of the top wiring layer. A barrier layer is formed over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. The conductive buffer layer is planarized to form a buffer pad in the buffer opening. A passivation layer is formed over the buffer pad and the buffer dielectric layer. A bond pad opening is formed in the passivation layer over at least a portion of the buffer pad. A bond pad support layer is formed over the buffer pad and the buffer dielectric layer. A bond pad layer is formed over the bond pad support layer. The bond pad layer and the bond pad support layer are patterned to form a bond pad and bond pad support.

Structure and method for fabricating a bond pad structure

A method of forming phoslon (PNO) comprising the following steps. A CVD reaction chamber having a reaction temperature of from about 300 to 600&#xb0; C. is provided. From about 10 to 200 sccm PHgas, from about 50 to 4000 sccm Ngas and from about 50 to 1000 sccm NHgas are introduced into the CVD reaction chamber. Either from about 10 to 200 sccm Ogas or from about 50 to 1000 sccm NO gas is introduced into the CVD reaction chamber. An HFRF power of from about 0 watts to 4 kilowatts is also employed. An LFRF power of from about 0 to 5000 watts may also be employed. Employing a phoslon etch stop layer in a borderless contact fabrication. Employing a phoslon lower etch stop layer and/or a phoslon middle etch stop layer in a dual damascene fabrication.

Use of phoslon (PNO) for borderless contact fabrication, etch stop/barrier layer for dual damascene fabrication and method of forming phoslon

A structure and method for an improved a bond pad structure. We provide a top wiring layer and a top dielectric (IMD) layer over a semiconductor structure. The buffer dielectric layer is formed over the top wiring layer and the top dielectric (IMD) layer. We form a buffer opening in the buffer dielectric layer exposing at least of portion of the top wiring layer. We form a barrier layer over the buffer dielectric layer, and the top wiring layer in the buffer opening. A conductive buffer layer is formed over the barrier layer. We planarize the conductive buffer layer to form a buffer pad in the buffer opening. We form a passivation layer over the buffer pad and the buffer dielectric layer. We form a bond pad opening in the passivation layer over at least a portion of the buffer pad. We form a bond pad support layer over the buffer pad and the buffer dielectric layer. We form a bond pad layer over the a bond pad support layer. The bond pad layer and the bond pad support layer are patterned to form a bond pad and bond pad support.

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Singapore, Singapore

Tan Juan Boon