National Science Council

Merck Patent Gmbh

Merck Patent Gesellschaft

Tan-Fu Lei

Chung-Len Lee

Chun-Yen Chang

Hsiao-Yi Lin

Tien-Sheng Chao

Shye-Lin Wu

Ming-Chi Liaw

Tung-Po Chen

Chun Yen Chang

Chao-Sung Lai

Yung-Hao Lin

Ci-Lin Pan

Juing-Yi Cheng

Jz-Jan Jeng

The present invention relates to a novel process for removing sidewall residue after dry-etching process. Conventionally, after dry-etching, photoresist and sidewall residues are removed by ozone ashing and hot sulfuric acid. Normally, they are hard to be removed completely. It was found in the present invention that the addition of fluorine-containing compound, preferably hydrogen fluoride and ammonium fluoride, in sulfuric acid results in complete removal of photoresist and sidewall residue without the need for stripper. The process is simple and does not affect the original procedures or the other films on the substrate. The present invention also relates to a novel solution for removing sidewall residue after dry-etching, which comprises sulfuric acid and a fluorine-containing compound, preferably hydrogen fluoride and ammonium fluoride, in the range of from 10:1 to 1000:1 by weight.

Solutions and processes for removal of sidewall residue after dry etching

A solution for cleaning silicon semiconductors or silicon oxides comprising H O , NH OH and at least one component A selected from the group consisting of fluoro-containing compounds and other ammonium salts than NH OH, wherein the weight ratio of H O to H O is between 1:5 and 1:50, the weight ratio of NH OH to H O is between 1:5 and 1:50, and the molar ratio of component A to NH OH is between 1:10 and 1:5000 is disclosed. The solution can achieve the efficacy equivalent to that of the conventional RCA two-step cleaning solution within a shorter time by one step and effectively remove contaminants such as organics, dust and metals from the surfaces of silicon semiconductors and silicon oxides without using strong acids such as HCl and H SO .

Solutions for cleaning silicon semiconductors or silicon oxides

A method for manufacturing a magnetic field transducing device is provided which includes (a) providing a substrate, (b) subjecting the substrate to a semiconductor device fabricating process in order to obtain a magnetic field transducer, (c) forming an oxide over the magnetic field transducer and (d) covering a magnetic film on the oxide in order to obtain the magnetic field transducing device. The semiconductor device fabricating process also includes (b1) utilizing a mask photolithography etching process to form an annular groove on the substrate, (b2) covering a first insulating layer on the substrate and using a second mask photolithography etching process to form a plurality of diffusing openings on the first insulation layer, (b3) forming extrinsic semiconductor region on the substrate exposed by the plurality of diffusing openings, (b4) forming a second insulation layer on the substrate, (b5) utilizing a third mask photolithography etching process to form a plurality of contacts on the extrinsic semiconductor region, and (b6) forming a conductor on the substrate in order to form a connecting line. The magnetic film is preferably made of Ni and Co.

Method of manufacturing magnetic field transducer with improved sensitivity by plating a magnetic film on the back of the substrate

Ultrahigh vacuum chemical vapor deposition (UHV/CVD) and chemical mechanical polishing (CMP) systems are used in a method which can fabricate polycrystalline silicon (poly-Si) and polycrystalline silicon-germanium (poly-Si.sub.1-x -Ge.sub.x) thin film transistors at low temperature and low thermal budget. Poly-Si and poly-Si.sub.1-x -Ge.sub.x can be deposited by UHV/CVD without any anneal step. And due to the ultra low base pressure and ultraclean growth environment, the As-deposited poly films have low defect densities. However, the surface morphology retards the usage of the fabricating top-gate poly TFT's. In this invention, the CMP system is used for improving the surface morphology, high performance poly-Si and poly-Si.sub.1-x -Ge.sub.x TFT's can be obtained.

Method to fabricate the thin film transistor

The present invention is related to a method for fabricating a silicon electronic device having a boron diffusion source layer, includes steps of: a) providing a silicon substrate; b) depositing a silicon layer on said silicon substrate; and c) growing a silicon-boron binary compound layer on said silicon layer as said boron diffusion source. When the Si-B layer is formed by a UHV/CVD process according to the present invention, the boron concentration in the Si-B binary compound layer will be extraordinary high (up to 1.times.10.sup.21 to 5.times.10.sup.22 atoms/cm.sup.3).

Method for forming silicon-boron binary compound layer as boron

A method for suppressing boron penetration in a PMOS with a nitridized polysilicon gate includes steps of 1) growing a layer of gate oxide on a substrate, 2) forming at least one first polysilicon layer on the gate oxide layer, 3) nitridizing the first polysilicon layer, 4) forming a second polysilicon layer on the first polysilicon layer; and 5) implanting B-containing ions into the first and second polysilicon layers for constructing a PMOS structure wherein the nitridizing step suppresses a boron ion from penetration into the substrate. The present invention is characterized in nitridation on a polysilicon gate instead of a gate oxide which can effectively suppress boron penetration, avoid drawbacks resulting from nitridizing a gate oxide, and moreover, improve the reliability of the device owing to the slight nitridation effect in the polysilicon gate and the gate oxide.

Method for suppressing boron penetration in PMOS with nitridized

Disclosed is a thin textured tunnel oxide prepared by thermal oxidation of a thin polysilicon film on Si substrate. Due to the rapid diffusion of oxygen through grain boundries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at grain boundries, a textured Si/SiO.sub.2 interface is obtained. The textured Si/SiO.sub.2 interface results in localized high fields and causes a much higher electron injection rate. EEPROM memory cells having the textured Si/SiO.sub.2 exhibit a lower electron trapping rate and a lower interface state generation rate even under high field operation.

Method of fabricating a textured tunnel oxide for EEPROM applications

A process is used to fabricate diodes having an emitter contacted p-n junction. A stack of n.sup.+ -type polysilicon layers are formed one upon the other upon a p-type silicon substrate. In an accordingly fabricated diode, native oxide layers that forms between the n.sup.+ -type polysilicon layer and the p-type substrate would be liable to be broken up, and thicker epitaxial layer would be formed between the same. The p-n junction is with a thickness of 0.05-0.2 .mu.m. As the diode is reverse-biased, for example at -5V, leakage current could be less than 1 n.ANG./cm.sup.2. The reverse-bias breakdown voltage could be larger than -100 V. When forward-biased, the ideality factor of the diode is close to unity.

Growing community of inventors

Hsinchu, Taiwan

Tan-Fu Lei