Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Tamotsu Ogata

Yutaka Inaba

Junichi Tsuchimoto

Kiyoshi Mori

Tomohiro Yamashita

Masamichi Fujito

Tomoya Saito

Hirofumi Tokita

Tatsuyoshi Mihara

Hiroshi Kurokawa

Hiroshi Umeda

Hiroaki Tamura

Toshifumi Iwasaki

A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

Semiconductor device and manufacturing method thereof

To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

Semiconductor device

A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1&#x3c;H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.

Semiconductor device and method of manufacturing semiconductor device

An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other. A second memory cell includes a second control gate electrode and a second memory gate electrode which are formed over the semiconductor substrate to be adjacent to each other. A width of a sidewall spacer formed on a side of the second memory gate electrode opposite to a side thereof where the second memory gate electrode is adjacent to the second control gate electrode is smaller than a width of another sidewall spacer formed on a side of the first memory gate electrode opposite to a side thereof where the first memory gate electrode is adjacent to the first control gate electrode. A threshold voltage of a first memory transistor including the first memory gate electrode in a neutral state is different a threshold voltage of a second memory transistor including the second memory gate electrode in the neutral state.

In a memory cell region of a semiconductor device, a memory active region is defined by an element isolation insulating film. In the memory cell region, the position of the upper surface of the element isolation insulating film is set to be lower than the position of the main surface of a semiconductor substrate. A buried silicon nitride film and an etching stopper film are formed over the element isolation insulating film. The position of the upper surface of the etching stopper film is higher than that of the upper surface of the element isolation insulating film defining a peripheral active region.

Over a semiconductor substrate, a memory gate electrode for a nonvolatile memory cell is formed via a first insulating film having an internal charge storage portion. A dummy control gate electrode is formed so as to be adjacent to the memory gate electrode via a second insulating film. The memory and the dummy control gate electrodes are made of different materials. A third insulating film is formed so as to cover the memory and the dummy control gate electrodes and then polished to expose the memory and the dummy control gate electrodes. Then, etching is performed under a condition in which the memory gate electrode is less likely to be etched than the dummy control gate electrode to remove the dummy control gate electrode. Then, in a trench as a region from which the dummy control gate electrode is removed, a control gate electrode for the memory cell is formed.

Manufacturing method of semiconductor device and semiconductor device

An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A memory cell of the nonvolatile memory includes a control gate electrode formed over a semiconductor substrate via a first insulating film and a memory gate electrode formed over the semiconductor substrate via a second insulating film to be adjacent to the control gate electrode via the second insulating film. The second insulating film includes a third insulating film made of a silicon dioxide film, a fourth insulating film made of a silicon nitride film over the third insulating film, and a fifth insulating film over the fourth insulating film. The fifth insulating film includes a silicon oxynitride film. Between the memory gate electrode and the semiconductor substrate, respective end portions of the fourth and fifth insulating films are located closer to a side surface of the memory gate electrode than an end portion of a lower surface of the memory gate electrode. Between the memory gate electrode and the semiconductor substrate, in a region where the second insulating film is not formed, another silicon dioxide film is embedded.

A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PWin a memory cell regionA in a semiconductor substrateand an MISFET arranged in a p-type well PW(active region) or an n-type well (active region) in a peripheral circuit regionA is constructed as follows. The surface of an element isolation region STIsurrounding the p-type well PWis set lower than the surface of an element isolation region STIsurrounding the p-type well PWor the n-type well (H&#x3c;H). By making the surface of the element isolation region STIreceded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STIis not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.

The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has first and second n type semiconductor regions in a semiconductor substrate, a control electrode formed over the substrate between the semiconductor regions via a first insulation film, and a memory gate electrode formed over the substrate between the semiconductor regions via a second insulation film having a charge accumulation part. The SSI method is used for write to the memory cell. During the read operation of the memory cell, the first and second semiconductor regions function as source and drain regions, respectively. The first width of the first sidewall spacer formed adjacent to the side surface of the memory gate electrode is larger than the second width of the second sidewall spacer formed adjacent to the side surface of the control gate electrode.

Semiconductor device and a manufacturing method thereof

To provide a semiconductor device having improved performance. A method of manufacturing the semiconductor device includes forming, after formation of a control gate electrode and a memory gate electrode, a conductive film on an insulating film made of a high-dielectric-constant film via a metal film; patterning the conductive film and thereby forming a gate electrode including the metal film and the conductive film in a high-voltage MISFET region, while forming a metal film portion and a conductive film portion in a low-voltage MISFET region; and then, removing the conductive film portion from the low-voltage MISFET region, forming another conductive film on the metal film portion, and forming a gate electrode including the metal film portion and the another conductive film.

Growing community of inventors

Tokyo, Japan

Tamotsu Ogata