Micron Technology Incorporated

Kabushiki Kaisha Toshiba

Tamotsu Murakoshi

Deepak Thimmegowda

Toru Tanzawa

Yoshiaki Fukuzumi

Koichi Kawai

Yoshihiko Kamata

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

Memory array having connections going through control gates

A microelectronic device comprises first digit lines, second digit lines, and multiplexer devices. The first digit lines are coupled to strings of memory cells. The second digit lines are coupled to additional strings of memory cells. The second digit lines are offset from the first digit lines in a first horizontal direction and are substantially aligned with the first digit lines in a second horizontal direction orthogonal to the first horizontal direction. The multiplexer devices are horizontally interposed between the first digit lines and the second digit lines in the first horizontal direction. The multiplexer devices are in electrical communication with the first digit lines, the second digit lines, and page buffer devices. Additional microelectronic devices, memory devices, and electronic systems are also described.

Memory devices including multiplexer devices, and related electronic systems

Microelectronic devices, and related memory devices and electronic systems

A semiconductor device includes a first power supply which is disposed in a first direction, a first pad array which is disposed in the first direction, adjacent to the first power supply line, a second power supply line extending in the first direction, a first buffer circuit which is disposed between pads included in the first pad array, a second pad array which is disposed in the first direction, a third power supply line extending along the second pad array such that the second pad array is interposed between the second power supply line and the third power supply line, and a second buffer circuit which is disposed between pads included in the second pad array, and which is operated by a voltage between the second and third power supply lines.

Semiconductor device

Growing community of inventors

Kawasaki, Japan

Tamotsu Murakoshi