Lsi Logic Corporation

Tammy T Huang

Alexander Y Tetelbaum

Maad A Al-Dabagh

Mike T Liang

Chun Chan

Wen-Chuan Hsu

A system, method and program product for designing integrated circuits. A design of an integrated circuit (IC) is analyzed to identify the longest path between each pair of registers. A crosstalk overhead is calculated for each identified longest path using a stochastic model. The crosstalk overhead of each longest path is added to selected path delays as an incremental port of register set up time. Any path wherein the sum of the path delay and crosstalk overhead exceeds a maximum accepted delay, i.e., where slack is less than or equal to zero is redesigned and the IC is then, placed and wired. The stochastic model may be a tree-like structure derived from several completed integrated circuit (IC) designs, in particular from cell placement and wiring for the completed IC. The tree-like stochastic model corresponds crosstalk delays to technology wire factors.

Integrated design system and method for reducing and avoiding crosstalk

A system, method and program for hierarchically designing integrated circuits(ICs). Potential sources of crosstalk are identified in the hierachical design and prior to and during placement and wiring while maintaining the hierachical structure. Blocks are placed and analyzed to determine if all blocks are well behaved and where necessary selectively re-organized to be well behaved. Blockages are inserted blocks to restrict top level wiring to avoid crosstalk. Orthogonal restrictions are placed on top level wiring as well as on top level wire lengths.

Provided is a technique for designing an integrated circuit die which includes a semiconductor layer, a primary metal layer, a horizontal metal layer and a vertical metal layer. Electronic components are laid out on the semiconductor layer, and a primary power distribution network for distributing power to the electronic components is laid out on the primary metal layer. Then, a uniform trunk width is calculated for all trunks in a power mesh based on a desired maximum voltage drop for the generated electronic component layout. Finally, horizontal power trunks are laid out on the horizontal metal layer and vertical power trunks are laid out on the vertical metal layer using the calculated uniform trunk width, so as to form the power mesh, and an electrical connection is specified between the power mesh and the primary power distribution network.

Integrated circuit design incorporating a power mesh

A method for optimizing routing mesh segment widths within limits imposed by voltage drop and metal migration requirements, beginning with an initial mesh comprising a plurality of horizontal segments forming rows and a plurality of vertical segments forming columns. First, a voltage drop and current density associated with each segment is determined. Then a first width for each segment is found by scaling each segment width using a voltage drop scaling factor so that the routing mesh has a maximum voltage drop that satisfies the voltage drop requirement. Next, widths for each segment are determined such that the metal migration requirement minus a margin is satisfied. Then the method ensures that each segment within each row, and each segment within each column, is not more than a first scaling factor wider than its neighboring segments. A second width for each segment is found by ensuring that each segment within each row is not more than a second scaling factor wider than segments at a same vertical position in neighboring rows, and each segment within each column is not more than the second scaling factor wider than segments at a same horizontal position in neighboring columns. The method then selects the larger of the first width and second width for each segment, determines the voltage drop and current density associated with each segment, and checks whether the voltage drop and metal migration requirements are violated. The above steps are repeated if the voltage drop or metal migration requirement is violated.

Method for optimizing routing mesh segment width

A system for modeling and estimating crosstalk noise and detecting false logic is provided. The noise is caused by culprit signal nets that are in a switching state and affect a victim net which is in a non-switching (DC) steady state. This estimated noise is evaluated against a predetermined threshold to determine whether any false logic results in the victim net.

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Fremont, CA, United States of America

Tammy T Huang