Renesas Electronics Corporation

Tamiyu Kato

Takanobu Suzuki

Akihiko Kanda

Tamaki Tsuruda

The present invention provides a semiconductor device including a nonvolatile memory of which the memory size of a data area and the memory size of a code area can be freely changed. The semiconductor device according to one embodiment includes a nonvolatile memory which can switch between a reference current reading system which performs data read by comparing a current flowing through a first memory cell as a read target and the reference current and a complementary reading system which performs data read by comparing currents flowing through a first memory cell and a second memory cell storing complementary data, as a read target.

Semiconductor device including nonvolatile memory configured to switch between a reference current reading system and a complimentary reading system

Semiconductor device including nonvolatile memory configured to switch between a reference current reading system and a complementary reading system

The trimming range of a reference current is extended larger than that of the related art. A semiconductor device includes a reference current generating circuit that generates a reference current. The reference current includes a first base current, a second base current base current, a second base current, a temperature compensating current, and a voltage compensating current. The first base current can be trimmed. The second base current flowing opposite to the first base current can be trimmed. The temperature compensating current flows in the same direction as the first base current and has higher temperature dependence than the first and second base currents. The voltage compensating current flows in the same direction as the first base current and depends on power supply voltages more than the base currents.

Semiconductor device

A memory array () includes a plurality of twin cells (), each of which is composed of a first memory element () and a second memory element () which are each electrically rewritable and configured to memorize binary data according to a difference in threshold voltages therebetween. A power supply control circuit (), upon receiving a request for erasing data in a twin cell, increases both the threshold voltage of the first memory element () and the threshold voltage of the second memory element () during the pre-writing, and after the pre-writing, differentiates the voltage of a first bit line (BL) which is connected to the first memory element () and the voltage of a second bit line (/BL) which is connected to the second memory element () during the application of erase pulse.

In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.

Semiconductor device with nonvolatile memory prevented from malfunctioning caused by momentary power interruption

A semiconductor device is provided which comprises a nonvolatile memory capable of storing complementary data and performing a more accurate blank check than ever before. A nonvolatile memory comprises a memory array having a plurality of twin cells arranged therein for storing complementary data, and first to third determination units. The first determination unit determines, for each of the twin cells selected by a selection circuit, whether or not a first condition that the threshold voltage of one memory cell is higher than a reference value commonly set and the threshold voltage of the other memory cell is lower than the reference value is satisfied. The second determination unit determines whether or not a second condition that all the selected twin cells satisfy the first condition is satisfied. The third determination unit determines, based on the determination result of the second determination unit, whether or not each of the selected twin cells is in a blank state.

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Tokyo, Japan

Tamiyu Kato