Mitsubishi Materials Silicon Corporation

Tamiya Karashima

Ken Nakajima

Hiroyuki Shiraki

Kazuhiro Ikezawa

A wafer of the invention is a silicon wafer of 0.02 &OHgr;cm or less in resistivity for deposition of an epitaxial layer, and the number of crystal originated particles (COP) and the number of interstitial-type large dislocation loops (L/D) are respectively 0 to 10 per wafer. A wafer of the invention is an epitaxial wafer having an epitaxial layer being 0.1 &OHgr;cm or more in resistivity and 0.5 to 5 &mgr;m in thickness formed on this wafer by means of a CVD method. A wafer of the invention is OSF-free and hardly makes traces of COP and L/D appear on the surface of an epitaxial layer when the epitaxial layer is formed. By heat treatment in a semiconductor device manufacturing process after the epitaxial layer is formed, BMDs occur uniformly and highly in density in the wafer and a uniform IG effect can be obtained in the wafer.

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Tokyo, Japan

Tamiya Karashima