Globalfoundries Inc.

International Business Machines Corporation

Globalfoundries U.S. Inc.

Tamilmani Ethirajan

Edward J Nowak

Brent A Anderson

Josef S Watts

Anupam Dutta

Ashwin Srinivas

Amit A Dikshit

Shrinivas J Pandharpure

Vaidyanathan T Subramanian

Haiting Wang

Zhenyu Hu

Ninad D Sathaye

Richard Francis Taylor, Iii

Wenjun Li

Janakiraman Viraraghavan

Cole E Zemke

Tung-Hsing Lee

Ananth Sundaram

Chen Perkins Yan

A simulation circuit, that simulates characteristics of transistors is produced to include: an isolation body resistor representing resistance of a channel isolation portion of a transistor; a main body resistor representing resistance of main channel portion of the transistor; an isolation transistor connected to the isolation body resistor; and a body-contact transistor connected to the main body resistor. Simulated data is generated by supplying test inputs to the simulation circuit, while selectively activating either the isolation transistor or the body-contact transistor. Test data is generated by supplying the test inputs to the transistors, and measuring output of the transistors. The simulated data is compared to the test data to identify data differences. The design of the transistors is changed to reduce the data differences. The generation of test data, comparing, and design changes are repeated, until the data differences are within a threshold.

Producing models for dynamically depleted transistors using systems having simulation circuits

One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

Lateral bipolar junction transistor device and method of making such a device

The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.

Cascode cell

The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Virtual drain for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches

Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (f) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (V); extracting a transconductance (G) from the first set of in-line DC parameters as a function of a gate-voltage (V) and the first drain-voltage (V); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (V); extracting a total gate capacitance (C) from the second set of in-line DC parameters as a function of the gate-voltage (V); and predicting the unity gain frequency (f) of the MOSFET based upon the extracted transconductance (G) and the extracted total gate capacitance (C).

Methods of predicting unity gain frequency with direct current and/or low frequency parameters

Disclosed are a system, a method and a computer program product for accurately modeling the performance of a body-contacted, asymmetric double gate, dynamically depleted (DD), semiconductor-on-insulator (SOI) field effect transistor (FET). This modeling can be performed, using iterative processing, to determine the conditions (e.g., back gate bias voltage, front gate bias voltage, body resistance and body charge) under which the FET channel region transitions from being in a partially depleted (PD) state such that the FET functions as a PD SOI FET to being in a fully depleted (FD) state such that the FET functions as a FD SOI FET. Once these conditions are known (i.e., once the model is generated), the DD SOI FET can be incorporated into top-level integrated circuit designs with specifications that either meet the conditions or do not meet the conditions, depending upon the desired function of the DD SOI FET within the integrated circuit.

Modeling the performance of a field effect transistor having a dynamically depleted channel region

Systems include, among other components, fixed and mobile sensors positioned within a pipe network containing a substance (such as a liquid, gas, or low-viscosity solid). In addition, systems include a mobile transceiver device positioned within the pipe network. The mobile transceiver device moves through the substance and the pipe network, and the mobile transceiver device is in wireless communication with the sensors. Systems also include a receiver that is external to the pipe network, and the receiver is in communication with the mobile transceiver device. In operation, the mobile transceiver device wirelessly receives sensor data from the sensors, the mobile transceiver device can aggregate the sensor data from multiple sensors, and the mobile transceiver device transmits the aggregated sensor data wirelessly to the receiver.

System managing mobile sensors for continuous monitoring of pipe networks

The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.

Hybrid circuit including a tunnel field-effect transistor

Disclosed are integrated circuit (IC) design methods, systems and computer program products. During IC design, an electrical netlist with built-in electrical resistance elements (i.e., electrical resistors) is extracted based on an IC design layout. A thermal netlist with built-in thermal resistance elements (i.e., thermal resistors) is automatically extracted based on the electrical netlist. This thermal netlist identifies thermal resistors, external thermal nodes and internal thermal node(s) and does so such that there is one-to-one mapping of the thermal resistors to electrical resistors in the electrical netlist, one-to-one mapping of the external thermal nodes to input, output and power supply nodes in the electrical netlist and one-to-one mapping of the internal thermal node(s) to element(s) (e.g., library and/or customized elements) in the electrical netlist. The electrical and thermal netlists are combined and simulations are performed on the combined electrical-thermal netlist in order to generate a thermal-aware performance model of the IC.

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Bengaluru, India

Tamilmani Ethirajan