Mediatek Corporation

Broadcom Corporation

Mediatek Singapore Pte. Ltd.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies General IP Pte, Ltd.

Tamer Mohammed Ali

Ali Nazemi

Henry Arnold Park

Ahmed Safwat Mohamed Aboelenein Elmallah

Afshin Momtaz

Mohammed Mohsen Abdulsalam Abdullatif

Ramy Awad

Mahmoud Reza Ahmadi

Jun Cao

Hassan Maarefi

Namik Kocaman

Siavash Fallahi

Burak Catli

E-Hung Chen

Amr Tarek Ahmed Abdelrazik Khashaba

Bo Zhang

Adesh Garg

Anand Jitendra Vasani

Meisam Honarvar Nazari

Jiawen Zhang

Hyo Gyuem Rhew

Miguel Gandara

Mohammed Abdul-Latif

Huan-Sheng Chen

Ahmed Othman Mohamed Mohamed ElShater

Ramy Mohamed Yousry Ahmed Elsayed Awad

Mazen Soliman Shawky Soliman

Shih-Hao Huang

Ahmed Othman Mohamed ElShater

Qaiser Nehal

Chien-Hua Wu

Miguel Francisco Gandara

Ahmed Othman Mohamed El Shater

The techniques described herein relate to analog-assisted feed-forward equalizers. An example apparatus includes a first charge element digital-to-analog converter (DAC) including a first plurality of charge storage elements configured to store first samples of charge based on respective first portions of a digital input signal, and generate, based on the first samples, a first analog output signal proportional to the first portions. The apparatus further includes a second charge element DAC coupled to the first charge element DAC and including a second plurality of charge storage elements configured to store second samples of charge based on respective second portions of the digital input signal, and generate, based on the second samples, a second analog output signal proportional to the second portions, and wherein the coupling of the first and second outputs generates a third analog output signal based on a combination of the first and second analog output signals.

Analog assisted feed-forward equalizer

The techniques described herein relate to digitally controlled delay line gain calibration using error injection. An example apparatus includes a digitally controlled delay line (DCDL) with a DCDL output and configured to: receive a clock signal to be output from a voltage-controlled oscillator, and delay the clock signal to generate a first delayed clock signal. The apparatus further includes an error injection circuit with a first error injection input and a second error injection input, the first error injection input coupled to the DCDL output. The apparatus additionally includes a phase controller with a phase controller output coupled to the second error injection input, the phase controller configured to, in response to a pseudorandom binary sequence signal, instruct the error injection circuit to generate a second delayed clock signal based on a delay of the first delayed clock signal.

Digitally controlled delay line gain calibration using error injection

A circuit or reducing fractional spurs comprises a digital to time converter (DTC) comprising multiple delay stages electrically coupled to one another in series, configured such that each delay stage is binary switched till the code exceeds cell range and then it is fully turned ON, and thereafter it is moved to the next stage, each delay stage comprising a digitally controlled delay line (DCDL) having code-dependent integrated nonlinearity (INL), with the maximal value of the INL occuring at a mid-code position; and an offset stage comprising the DCDL electrically coupled to the DTC in series, configured to generate random codes for each required time delay of the DTC to ensure the probability of landing at the mid-code position is reduced and landing point is kept as far away as possible from the mid-code position for every required time delay, thereby improving the INL and the fractional spurs.

Multi-stage digitally controlled delay line linearity enhancing by redundancy and randomization

A system to operate as a phase locked loop (PLL) includes a frequency synthesizer in a feedback path of the PLL and a delay line arranged to receive an output of the frequency synthesizer. A retimer subsystem is arranged to receive the output of the frequency synthesizer. A digitally controlled delay line (DCDL) is arranged to receive an output of the retimer. A phase detector is arranged to receive an output of the delay line and an output of the DCDL and to provide an error signal indicating a difference in phase of the output of the delay line relative to the output of the DCDL. A controller causes closed loop operation of the PLL during a normal operational mode and open loop operation during a calibration mode during which gain of the DCDL, defining a relationship between a control code and a resulting delay, is calibrated.

Gain calibration of digitally controlled delay line

The techniques described herein relate to duty cycle error calibration. An example apparatus includes a multi-modulus divider (MMD) circuit configured to receive a first digital code corresponding to a first time delay and included in a first plurality of digital codes associated with a first range of time delays, divide a clock signal by a divisor to generate a divided clock signal, and delay the divided clock signal by the first time delay to generate a delayed clock signal. The apparatus may further include a digitally controlled delay line (DCDL) circuit configured to receive a second digital code corresponding to a second time delay and included in a second plurality of digital codes associated with a second range of time delays, and delay the delayed clock signal by the second time delay to generate a feedback clock signal to reduce a difference between the feedback and a reference clock signal.

Digital phase-locked loop and related merged duty cycle calibration scheme for frequency synthesizers

The techniques described herein relate to systems, apparatus, articles of manufacture, and methods for optimum loop gain calibration for clock data recovery and phase locked loop. An example apparatus includes a phase detector with a phase detector output and configured to generate an error signal representative of a difference between an input signal and a feedback signal. The apparatus further includes a calibrator circuit with a calibrator input coupled to the phase detector output and configured to determine correlation value associated with the error signal, and determine a gain value based on an adjustment of an absolute value of the correlation value by a pseudorandom binary sequence signal.

Apparatus and method for optimum loop gain calibration for clock data recovery and phase locked loop

Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state ('enabled') or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.

Wideband signal attenuator

A continuous time linear equalizer (CTLE) includes a first circuit path having a step response that increases from an first initial value to a steady state value higher than the first initial value. The CTLE also includes a second circuit path in parallel with the first circuit path, the second circuit path having a step response that increases from a second initial value to a peak and subsequently falls to second steady state value that is approximately equal to the second initial value. The CTLE is configured to combine an output of the first circuit path and an output of the second circuit path.

Continuous time linear equalizer with a plurality of signal paths

A low power receiver having a feedforward equalization, FFE, based continuous time linear equalizer, CTLE. The FFE CTLE comprises: an input for receiving an input signal; a main first path operably coupled to the input and comprising a source-follower transistor arranged to apply a scaling factor to the received input signal; a second path operably coupled to the input and comprising a delay arranged to apply a delay to the received input signal and a common source transistor common source transistor arranged to apply a scaling factor to the received delayed input signal, wherein the source-follower transistor and the common source, CS, transistor are connected as a single SF-CS stage whose output is arranged to subtract the output of the common source transistor from an output of the source-follower transistor.

Low power receiver with equalization circuit, communication unit and method therefor

A receiver front-end includes a first variable-gain amplifier that performs attenuation; a continuous time linear equalizer coupled to the input or output of the first variable-gain amplifier, wherein a combination of the first variable-gain amplifier and the continuous time linear equalizer produces a processed signal; a plurality of track-and-hold circuits that sample the processed signal in an interleaved manner; and a plurality of second variable-gain amplifiers receiving input signals from the plurality of track-and-hold circuits respectively.

Hybrid receiver front-end

Systems and methods for detecting the presence and/or location of defects (e.g., incomplete solders, broken cables, misconnections, defective sockets, opens, shorts, etc.) along electrical lines are described. The systems and methods described herein may use time-domain reflectometry (TDR), a measurement technique used to determine the characteristics of electrical lines by observing reflected waveforms. TDR may be performed in some embodiments by determining the times when a first event and a second event occur, and by determining the space traveled by a probe signal based on these times. The first event may occur when a first signal transition crosses a first threshold and the second event may occur when a second signal transition crosses a second threshold, where the second signal transition may arise in response to the first signal transition reflecting against a defect along the electrical line.

Systems and methods for on-chip time-domain reflectometry

Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.

Circuits for delay mismatch compensation and related methods

System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.

Systems for reducing pattern-dependent inter-symbol interference and related methods

A line receiver is described. The line receiver may be configured to receive signals transmitted via a communication channel, such as a metal trace on a printed circuit board or a cable. The receiver may comprise a buffer and circuitry for enhancing the trans-conductance gain of the buffer. By enhancing the trans-conductance gain of the buffer, linearity may be improved and susceptibility to process and temperature variations may be limited. Enhancement of the trans-conductance gain may be performed using feedback circuitry coupled to the buffer. The receiver may further comprise mirror circuitry configured to provide a desired current to the load. The receiver may further comprise a gain stage for setting the gain of the receiver to a desired level.

Growing community of inventors

Irvine, CA, United States of America

Tamer Mohammed Ali