Samsung Electronics Co., Ltd.

Applied Materials, Inc.

Intel Corporation

Tameesh Suri

Manu Awasthi

Vijay Balakrishnan

Narges Shahidi

Myron O Shak

Naveed Zaman

Bilal Shafi Sheikh

Bob Brennan

Suhas

Aneesh Aggarwal

Arash Rezaei

Ashwini Batrahalli

A router may include input buffers that receive a packet being transmitted from a source to a destination, a state generator that determines a state for the packet, and a memory representing weights for actions corresponding to possible states. The memory may be configured to return an action corresponding to the state of the packet, where the action may indicate a next hop in the route between the source and the destination. The router may also include reward logic configured to generate the weights for the plurality of actions in the memory. The reward logic may receive a global reward corresponding to the route between the source and the destination, calculate a local reward corresponding to next hops available to the router; and combine the global reward and the local reward to generate the weights for the plurality of actions in the memory.

Router architecture for multi-dimensional topologies in on-chip and on-package networks

A network-on-package (NoPK) for connecting a plurality of chiplets may include a plurality of interface bridges configured to convert a plurality of protocols used by the plurality of chiplets into a common protocol, a routing network configured to route traffic between the plurality of interface bridges using the common protocol, and a controller configured to program the plurality of interface bridges and the routing network based on types of the plurality of chiplets connected to the NoPK. The NoPK may provide a scalable connection for any number of chiplets from different ecosystems using different communication protocols.

Scalable network-on-package for connecting chiplet-based designs

According to one general aspect, an apparatus may include a memory, an erasure-based, non-volatile memory, and a processor. The memory may be configured to store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The erasure-based, non-volatile memory may be configured to store information, at respective memory addresses, in an encoded format. The encoded format may include more bits than the unencoded version of the information and the encoded format may allow the information be over-written, at least once, without an intervening erase operation. The processor may be configured to perform garbage collection based, at least in part upon, the rewriteable state associated with the respective memory addresses.

Block cleanup: page reclamation process to reduce garbage collection overhead in dual-programmable NAND flash devices

A Solid State Drive (SSD) () is disclosed. The SSD () may include storage () for data, and reception circuitry () to receive various instructions and data. The reception circuitry () may receive an instruction () from a host machine () to perform garbage collection, along with a selected P/E strategy (). The SSD () may include garbage collection logic () to perform garbage collection, possibly with a delayed Program operation if an adaptive P/E strategy () is selected. The SSD () may also include a mapping table () that may identify which pages were not Programmed before victim blocks () were erased, and therefore require replication during a delayed Program operation.

Dynamic garbage collection P/E policies for redundant storage blocks and distributed software stacks

According to one general aspect, an apparatus may include a host interface, a memory, a processor, and an erasure-based, non-volatile memory. The host interface may receive a write command, wherein the write command includes unencoded data. The memory may store a mapping table, wherein the mapping table indicates a rewriteable state of a plurality of memory addresses. The processor may select a memory address to store information included by the unencoded data based, at least in part, upon the rewriteable state of the memory address. The erasure-based, non-volatile memory may store, at the memory address, the unencoded data's information as encoded data, wherein the encoded data includes more bits than the unencoded data and wherein the encoded data can be over-written with a second unencoded data without an intervening erase operation.

Multi-bit data representation framework to enable dual program operation on solid-state flash devices

An embodiment includes a storage device, comprising: a memory; and a controller including a memory interface coupled to the memory, the controller configured to: receive write data to write to an address associated with first data stored in the memory and a first differentially compressed value stored in the memory; calculate a second differentially compressed value based on the write data and the first data; store the second differentially compressed value in the memory; and change the association of the address to reference the second differentially compressed value instead of the first differentially compressed value.

Versioning storage devices and methods

Inventive aspects include a high bandwidth peer-to-peer switched key-value system, method, and section. The system can include a high bandwidth switch, multiple network interface cards communicatively coupled to the switch, one or more key-value caches to store a plurality of key-values, and one or more memory controllers communicatively coupled to the key-value caches and to the network interface cards. The memory controllers can include a key-value peer-to-peer logic section that can coordinate peer-to-peer communication between the memory controllers and the multiple network interface cards through the switch. The system can further include multiple transmission control protocol (TCP) offload engines that are each communicatively coupled to a corresponding one of the network interface cards. Each of the TCP offload engines can include a packet peer-to-peer logic section that can coordinate the peer-to-peer communication between the memory controllers and the network interface cards through the switch.

High bandwidth peer-to-peer switched key-value caching

Mechanisms for predicting whether a memory access may be a page hit or a page miss and applying different page policies (e.g., an open page policy or a close page policy) based on the prediction are disclosed. A counter may be used to determine a hit rate (e.g., a percentage or a ratio of the number of memory accesses that are page hits). The processing device may apply different page policies based on the hit rate. A memory access history (that includes data indicating a sequence or list of memory accesses) may be used to identify a counter from a plurality of counters. The processing device may apply different page policies based on the value of the counter (e.g., based on whether the counter is greater than a threshold).

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San Jose, CA, United States of America

Tameesh Suri