Silicon Storage Technology, Inc.

Intel Corporation

Altera Corporation

Sae Magnetics (h.k.) Limited

Lewiz Communications

Tam Minh Nguyen

Thuc Tran Bui

Hung Quoc Nguyen

Sang Thanh Nguyen

Douglas J Lee

Marc A Finot

Jeffrey A Bennett

Rickie Charles Lake

Robert Kohler

Hung Thanh Nguyen

Xiaowei Yao

Richard Zimering

Cindy Ho Malamy

Kyle McMartin

Conrado Canlas Canio

Chong H Lee

Michael S Briner

Loc Bao Hoang

Divya Vijayaraghavan

Ning Xue

Kazumasa Yasuda

Michael Menghui Zheng

Niraj Mahadev

Winston Jose

Bao Nguyen

Rudy Ayala

Chinh Le

Jih-Min Niu

Jih Min Niu

Mike Briner

David Sweetman

A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals received in serial format and reconstitutes the address, data and command signals, and has an output. A command circuit receives the output of the input buffer and stores the command signals therefrom. An address circuit receives the output of the input buffer and stores the address signals therefrom. A data buffer circuit receives the output of the input buffer and stores the data signals therefrom. An array of non-volatile memory cells stores data from and provides data to the data buffer in response to address signals from the address decoder. A state machine is connected to the command circuit and controls the array of non-volatile memory cells. An output buffer receives data from the data buffer circuit and provides data to the interface circuit.

Non-volatile memory device having high speed serial interface

A programmable logic integrated circuit device ('PLD') includes high-speed serial interface ('HSSI') circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).

Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device

A system and method for producing micro-texture on a slider substrate using chemical & mechanical polishing techniques is described. In certain embodiments of the present invention, this is accomplished by a method comprising formulating an abrasive slurry solution of predetermined acidity (or pH value), treating a chemical mechanical polishing pad with the abrasive slurry, disposing magnetic heads on the chemical mechanical polishing pad and lapping and grinding the magnetic heads for a predetermined period of time. In certain embodiment of the present invention the lapping and grinding of the magnetic heads are accomplished using an apparatus comprising an abrasive slurry solution of predetermined acidity (pH value), a chemical mechanical polishing pad treated with the abrasive slurry solution, wherein the magnetic heads are attached to a fixture capable of disposing the heads on the chemical mechanical polishing pad.

Method and apparatus for producing micro-texture on a slider substrate using chemical and mechanical polishing techniques

A circuit package includes a substrate having an opening and a single unitary heat sink adapted to effectively dissipate heat is positioned in the opening to expose top and bottom surfaces which are respectively coplanar with top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.

Circuit package and method of plating the same

A PCI card comprises upper and lower surfaces; a mounting hole defining first and second holes, the first hole having a larger diameter than the second hole; a stud that is inserted into the mounting hole and flushed to the upper surface; and a port connector provided on the stud to minimize space consumption. The first and second holes are concentric circles. Alternatively, the first and second holes are not perfect circles.

Low-profile PCI adapter cards with high port counts

A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.

Predetermined data is stored in first and second predetermined locations of a memory. The first location may be in a first part of the memory, and the second location may be in a redundant part of the memory. At power up or reset, the first predetermined location of the memory successively is read and compared to data stored in a register until the comparison indicates a match for a predefined number of consecutive reads and comparisons. The successive reading may be stopped if the number of comparisons indicating a failure equals another predefined number of times. The data stored in the second predetermined location also is read. This data may be compared to the data previously read from the second predetermined location. The reading and comparing from the first predetermined location and the reading from the second predetermined location are continued until the number of times data is read from the second predetermined location equals a third predetermined number. The voltage signal is then determined to be valid after sufficient successive reads of the first predetermined location of the memory.

Embedded recall apparatus and method in nonvolatile memory

A flash memory comprises an address bus, a data bus, control lines, and an array of addressable nonvolatile memory cells, connected to the address bus and the data bus. A latch, activated by control signals, stores signals supplied from the address bus or the data bus. A decoder decodes the signal stored in the latch, and in response to a first signal decoded for partitioning the array of memory cells into a plurality of first sectors each having a first size, and in response to a second signal decoded for partitioning the array of memory cells into a plurality of second sectors each of a second size, different from the first size. A control circuitry controls the erasure of a first or a second sector of the memory array in response to the first or second signal decoded.

Flash memory with alterable erase sector size

A power reset signal generator provides a power reset signal having a minimum predetermined pulse width independent of the ramp time of the applied power.

Power on circuit for generating reset signal

An integrated circuit for concurrent flash memory. The circuit has an uneven array architecture including a pair of arrays of a first size, and a pair of arrays of a second size. The arrays and are cooperatively linked in a manner which allows certain arrays to be read while other arrays are concurrently programmed or erased. The uneven array architecture of circuit provides increased flexibility of bank size combinations for concurrent read and program/erase operation.

Integrated circuit for concurrent flash memory with uneven array architecture

A reprogrammable fuse has a pair of non-volatile memory cells differentially programmed. The pair of non-volatile memory cells are connected to a pair of bitlines and through a pair of switches to a precharging voltage. The switches are controlled by a precharging and equalization signal, which when activated, serves to precharge the bitlines. The charged bitlines are then connected to the pair of differentially programmed non-volatile memory cells and one of the bitlines is discharged faster than the other. The resultant output is taken from one of the bitlines.

Reprogrammable fuse and method of operating

A control circuit for a non-volatile memory array having a plurality of sectors, comprises a plurality of mirror circuits connected in parallel. Each mirror circuit comprises a first transistor and a common transistor. The common transistor is common to all of the mirror circuits connected to all of the sectors. A charge pump supplies voltage to the node that connects between the first transistor and the mirror transistor. A current limiter circuit limits the amount of current flowing through the common transistor. The control circuit limits the amount of current that can flow through a defective sector and controls the rate at which voltage from the charge pump is supplied to each of the sectors.

Control circuit for a non-volatile memory array for controlling the ramp rate of high voltage applied to the memory cells and to limit the current drawn therefrom

The self-latching data circuit reads data from a pair of memory cells and latches the read data in response to a single transition of an enable signal. The self-latching data circuit includes a pair of PFETS that pull first and second nodes to a power supply voltage in response to an enable signal being in a low state. The self-latching data circuit also includes a pair of series connected PFET and NFETS in which the first and second data nodes are formed of the node connecting the series PFET and NFET together. In response to the enable signal transitioning to a high state, the memory cells are read and the contents thereof are applied to the first and second data nodes. The signal of one data node is applied to the gates of the transistors of the transistor pair corresponding to the other data node. This feedback causes the data cell having the greatest current draw to pull the other data node to the power supply level and pull itself to a zero voltage level to thereby latch the data. In the self-latched condition, the self-latching data circuit has minimal power draw.

Timing independent current comparison and self-latching data circuit

A charge pump circuit is provided which includes a plurality of successively coupled charge pump stages. Each of these successively coupled charge pump stages receives at least one input signals and at least one clock input signals, and in accordance therewith, conveys at least one output signal. Significantly, at least one output signal of a prior charge pump stage is substantially equal to at least one input signal of a next adjacent charge pump stage, so that the prior adjacent charge pump stage will be effectively shut off, so that reverse current flow can be prevented through the charge pump circuit.

Growing community of inventors

Cupertino, CA, United States of America

Tam Minh Nguyen