Marvell International Limited

Talip Ucar

Pierte Roo

A level shift circuit includes a first latch circuit configured to receive a clock signal, a digital data signal, a first supply voltage, and a second supply voltage, and generate a first output signal based on the digital data signal. The first output signal has a first voltage level corresponding to the first supply voltage, and a second voltage level corresponding to the second supply voltage. At least one capacitor is configured to receive the first output signal, and retain a voltage value corresponding to the output signal. A second latch circuit is configured to receive the voltage value, a third supply voltage, and a fourth supply voltage, and generate a second output signal based on the voltage value. The second output signal has a third voltage level corresponding to the third supply voltage and a fourth voltage level corresponding to the fourth supply voltage.

Circuits and methods for level shifting a signal

A circuit includes a first current source, a second current source, a third current source and a fourth current source. A load includes a first terminal connected to a first node between the first current source and the second current source and a second terminal connected to a second node between the third current source and the fourth current source. A bias control module includes a first output configured to output a first bias signal to the first and fourth current sources and a second output configured to provide a second bias signal to the second and third current sources. A capacitance is connected to the first and second outputs of the bias control module.

Kickback cancellation in class B type circuits using AC coupling

In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.

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San Francisco, CA, United States of America

Talip Ucar