Semiconductor Manufacturing International (shanghai) Corporation

Talee Yu

Chi Liu

Hellen Cheng

An integrated circuit device comprising an improved bonding pad structure. The device has a semiconductor substrate. A plurality of active MOS devices are formed on the semiconductor substrate. The device has an interlayer dielectric layer overlying the plurality of active MOS devices and at least one single metal bonding pad formed on the interlayer dielectric layer and directly over at least one of the active devices. At least four edge regions are formed on a square shape of the at least one single metal bonding pad. An angled cut region is formed on each of the four edge regions. The device has a buffer metal layer free region located between the plurality of active MOS devices and the at least one single metal bonding pad. The buffer metal layer free region does not have a buffer metal layer in the interlayer dielectric layer.

Device under bonding pad using single metallization

Techniques for ESD protection are provided. An ESD protection device includes a first well region and a second well region disposed in a semiconductor substrate, with an isolation region therebetween. N+ implant regions are disposed in the second well region and are coupled in common at a first node. NLDD regions are disposed between the N+ implant regions, and pocket implants underlie each of the NLDD regions. Current discharge paths are defined by corresponding NLDD regions and pocket implants when a voltage of the first node exceeds a breakdown voltage. In a specific embodiment, the breakdown voltage is less than a breakdown voltage for a logic gate oxide.

Low voltage trigger and save area electrostatic discharge device

Techniques to avoid crowbar current are provided. An integrated circuit according to an embodiment of the present invention includes a first node having a first supply voltage level. A first level shift circuit is connected between the first node and a first path. A second level shift circuit is connected between the first node and a second path. The first path includes an even number of inverter stages, while the second path includes an odd number of inverter stages. The first and second level shift circuits are configured to output a signal at the second supply voltage level. The integrated circuit also includes a PMOS transistor and an NMOS transistor connected in series between a second node having the second supply voltage level and a reference voltage. A gate of the PMOS transistor is connected to the first path, and a gate of the NMOS transistor connected to the second path. An I/O pad connected between the PMOS and NMOS transistors has high impedance during a power-on period when the second node is powered up before the first node. In other specific embodiments, the inverter stages of the first path and the second path can be replaced with pull-up or pull-down circuits, respectively.

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Shanghai, China

Talee Yu