International Rectifier Corporation

Apple Inc.

Linear Technology Corporation

Talbott Mead Houk

Thomas J Ribarich

Mark A Yoshimoto

Jamie L Langlinais

Dana S Wilhelm

Rajarshi Paul

Eugene Cheung

Parin Patel

Bruno Charles Nadd

Jay B Fletcher

Jonathan Mark Audy

Sanjay Pant

Peter N Wood

Siarhei Meliukh

Nathan F Hanagami

Nikola Jovanovic

Di Zhao

Wenxun Huang

Floyd L Dankert

Alessandro Molari

Damon Lee

Hartmut Sturm

Ludmil N Nikolov

Tristan R Hudson

Muthu Subramanian

Goran Perica

Seyedeh Maryam Mortazavi Zanjani

Nicola Florio

Chad L Olson

John J Sullivan

Jonathan A Dutra

Joseph Duncan

Gregory P Dittmer

Eugene L Cheung

The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.

Wakeup circuit

A power conversion circuit providing a regulated output voltage to a load can include a switching regulator with an input configured to be coupled to an input voltage source and an output configured to be coupled to the load. The power conversion circuit can further include a metered charge transfer converter, such as a charge pump or a switched or pulsed current source, having an input configured to be coupled to an input voltage source and having an output configured to be coupled to the load. A controller coupled to the metered charge transfer converter can be configured to operate the metered charge transfer converter to deliver energy to the load responsive to a dip of the regulated output voltage below a threshold caused by an increase in current drawn by the load. The metered charge transfer converter may be located closer to the load than the switching regulator.

Metered charge transfer assisted switching regulators

The embodiments discussed herein relate to systems, methods, and apparatus for providing a charger capable of adaptively handling a range of power inputs. The charger can selectively activate different control switches within the charger in order to more efficiently use current supplied to the charger. When a low power input is provided to the charger, the charger can reduce the number of active control switches being used to provide a voltage output from the charger. In this way, the capacitance required to toggle the control switches can be reduced. When a high power input is provided to the charger, the number of active control switches can be increased in order to increase a total amount of charge that can be provided from the charger, thereby reducing charge times for batteries.

Unified high power and low power battery charger

A power conversion circuit has multiple phases wherein each of the phases has an inductor coupled to a power switch circuit and is coupled to an output node. A power conversion controller controls the switching of one or more of the phases to yield a regulated voltage on the output node. The controller uses a variable inductor current limit for one or more designated phases, and temporarily increases the variable inductor current limit during a transient condition. Other embodiments are also described and claimed.

Multiphase power conversion using skewed per-phase inductor current limits

Control circuitry controls a boost regulator during a start-up period. The control circuitry may comprise an oscillator for generating a clock signal. The oscillator may be configured for ramping up a frequency of the clock signal in accordance with an voltage to be applied to the oscillator and varied during the start-up period. The control circuit may further include a switching circuit configured for controlling a power switch of the boost regulator in response to the clock signal from the oscillator. The switching circuit can control the power switch to have an on-time which is largely independent of the operating frequency of the oscillator. The voltage to be applied to the oscillator may have the same initial voltage level upon startup of the control circuit, independent of an output voltage of the boost regulator.

DC/DC converter startup with frequency ramping

An analog control circuit is coupled to an apparatus having a variable characteristic over an operating range. A sensing circuit is coupled to the apparatus and the control circuit during the range of operation of the apparatus and is operative to sense the variable characteristic. The operating parameter of the apparatus is controlled to be set at a level corresponding to a prescribed criterion, which may be a maximum or minimum, of the characteristic sensed over the range of operation.

System and method for tracking a variable characteristic through a range of operation

Pulse width modulation of the connection of a load output terminal to a power supply terminal is effected. In response to a first level of the pulse width modulated signal, the load is disconnected from the power supply terminal, steady-state load voltage is preserved on a capacitor connected between a load output terminal and a power supply terminal, and steady-state load current information is held on a capacitor within the feedback loop. In response to a second level of the pulse width modulated signal, the load is reconnected to the power supply terminal, and load voltage and current instantaneously resume at their correct steady-state values.

Switch-mode power supply voltage regulator and methodology

The present invention provides methods and circuits for protecting power converters from over-current conditions that, in one embodiment, (1) reduce average inductor current to a steady-state threshold during a transient phase and regulate average inductor current in steady-state regulation approximately at the steady-state threshold; and (2) reduce instantaneous inductor current after the instantaneous inductor current exceeds a maximum instantaneous threshold during the transient phase.

Methods and circuits for programmable current limit protection

A circuit which detects near or below resonance operation of a fluorescent lamp being driven with a half-bridge circuit and which deactivates the half-bridge circuit before any damage to the circuit can result. In the circuit of the present invention, the voltage across a sense resistor disposed either the lower transistor switch and ground, or between the lower lamp filament and ground, is compared against a predetermined reference voltage to generate an output comparison signal. The output comparison signal is gated to the turn-off edge of the lower MOSFET (in the case of the sense resistor disposed between the lower MOSFET and ground) or to the turn-off edge of the upper MOSFET (in the case of the sense resistor between the lower lamp filament and ground) to generate a signal for shutting down the half-bridge circuit in the event of near or below resonance operation of the lamp resonant circuit.

Circuit for detecting near or below resonance operation of a fluorescent lamp driven by half-bridge circuit

A ballast controller integrated circuit which executes a specific set of instructions via an integrated state diagram architecture to control the fluorescent lamp and protect the ballast. The state diagram architecture controls powering up and down of the IC and the half-bridge circuit driven by the IC, preheating and striking of the lamp, running of the lamp, sensing for numerous possible fault conditions, and recovering from these fault conditions based on the normal maintenance of a lamp.

Fully integrated ballast IC

A MOS gate drive (MGD) integrated circuit drives a pair of MOS gated power semiconductor devices such as are used in a half bridge circuit to drive a load in a resonant power supply circuit or to drive a gas discharge lamp in a ballast circuit. The gate drive circuit includes a protection circuit which protects against damage to the components of the driver circuit when a lamp fails or is removed by disabling both of the driver outputs. When the lamp is replaced, the gate drive circuit restarts the lamp driver circuit without cycling the lamp power switch. The protection circuit disables the driver outputs when a low logic level signal falls below a threshold voltage. The lamp driver circuit is restarted when the low logic level signal exceeds the threshold voltage.

Ballast IC with shut-down function

A protection circuit for preventing non zero-voltage switching of a lamp resonant output circuit driven by upper and lower half-bridge switches. The protection circuit includes a sense resistor disposed between the lower half bridge switch and ground for developing a voltage corresponding to the current flowing through the lower switch. A comparator compares the voltage developed across the sense resistor against a fixed reference voltage and generates an output indicative of a non zero-voltage switching condition when the voltage across the sense resistor exceeds the fixed reference voltage. A latch is connected to the output of the comparator and generates a latch output signal which disables the generation of drive signals to the upper and lower switches in the event of a non zero-voltage switch condition.

Non zero-voltage switching protection circuit

A circuit for and a method of driving first and second power transistors arranged in series in a half-bridge configuration provides for soft turn-on of the power transistors when there is a change of state in the input voltage. When the input voltage initially changes state, the gate drive voltage of one of the power transistors is raised to a voltage barely above its threshold value for a predetermined interval. The gate drive voltage of this power transistor is then raised to the supply voltage value. When the input voltage again changes state, the transistor is turned off, and the other transistor is turned on in a similar manner. As a result, when one of the transistors is turned on, current transients in the other transistor is reduced.

Soft-switching driver output stage and method

A monolithic MOS gate driver chip is described for driving high side and low side power MOSFETs in a gas discharge lamp ballast circuit. The chip includes a timer circuit for generating a square output at the natural frequency of resonance of the lamp ballast. Dead time circuits are provided in the chip to prevent the simultaneous conduction of both high side and low side MOSFETs. The chip may be housed in an eight pin DIP package.

Growing community of inventors

Monte Sereno, CA, United States of America

Talbott Mead Houk