Intel Corporation

Tal Gat

Simcha Gochman

Michael Kagan

Mohammad A Abdallah

Itamar S Kazachinsky

Franck Sala

Hon Shing Lau

Eran Altshuler

Shou-Wen Fu

Aviel Timor

In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such as shuffle and shift operations may be performed in the common execution unit in a single cycle. Other embodiments are described and claimed.

Execution unit for performing shuffle and other operations

A system, method and device for storing branch predictions in a queue that may be connected to a branch prediction unit, and for delivering the stored predictions to an instruction fetch unit. A look up may be made of for example two sequential lines, and for example a segmented cache of a branch prediction unit may generate predictions of an address having an even numbered index by referring to for example a first side of the cache, and an address with an odd numbered index by referring to for example a second side of the cache. Branch predictions for two sequential lines may be generated during for example a prediction period such as two clock cycles. In some embodiments, a next instruction pointer of a branch prediction unit may be independent or decoupled from of a next instruction pointer of an instruction fetch unit.

System, method and device for queuing branch predictions

A loop detector with an array to store a counter of loop iterations, where the number of entries in the array may be, for example, smaller than the number of entries in the loop detector. Entries in the array may, for example, be associated with more than one entry in the loop detector. The array may store, for example, a counter of speculative iterations of a loop or, for example, a number of actual iterations of a loop.

System, device and method of maintaining in an array loop iteration data related to branch entries of a loop detector

An improved cache memory for use with a microprocessor. A line buffer which stores a tag and offset field and the corresponding line of data is employed. Valid bits are associated with different potions of the data stored in the line buffer. Thus during a line fill, by way of example, an instruction may be read from the line buffer before the entire line is filled from main memory.

Line buffer for cache memory

An improvement in a microprocessor permitting the selection of write-back, write-through or write-once protocols is disclosed. A pin is connected to either ground or Vcc potential to select either the write-through or write-back protocols. When this pin is connected to the read/write line, the write-once protocol is selected. Interconnection between two processors is described which permits the processors to operate in a write-once protocol with a minimum of glue logic.

Growing community of inventors

Haifa, Israel

Tal Gat