Ps4 Luxco S.a.r.l.

Elpida Memory, Inc.

Other

Takuyo Kodama

Yuki Nakamura

Kosuke Goto

Yoji Idei

A method for outputting data in a semiconductor device includes receiving an external clock signal, synchronizing, in a delay locked loop of the semiconductor device, a first internal clock signal to the external clock signal during a read period, synchronizing, in the delay locked loop, a second internal clock signal to the external clock signal during an active period, the second internal clock signal having a period longer than the first internal clock signal, and outputting data synchronized with the first internal clock signal during the read period.

Semiconductor device outputting read data in synchronization with clock signal

Such a device is disclosed that includes an internal voltage generating circuit generating an internal voltage by lowering an external potential and supplying the generated internal voltage to a power supply line, a switch being connected between a grounding wire to which a ground voltage is supplied and the power supply line, and a one-shot signal generating unit controlling turning on and off of the switch, wherein the one-shot signal generating unit brings the switch into conduction synchronously with start of generating the internal voltage by the internal voltage generating circuit.

Semiconductor device generating internal voltage

Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal.

Semiconductor device periodically updating delay locked loop circuit

Such a device is disclosed that includes a clock generation circuit generating a first clock signal and having an output node, and a drive circuit coupled to the output node of the clock generation circuit. The clock generation circuit outputs the first clock signal from the output node to the drive circuit in a clock output mode, fixes a potential of the output node to a first level in a first clock stop mode, and fixes the potential of the output node to a second level that is different from the first level in a second clock stop mode.

Semiconductor device generating a clock signal when required

Disclosed herein is a device that includes a clock generation circuit that generates an internal clock signal during a normal operation and stops generation of the internal clock signal during a wafer-level burn-in test, a clock tree line that transmits the internal clock signal, and a selector that supplies a dummy clock signal, which is different from the internal clock signal, to the clock tree line during the wafer-level burn-in test.

Semiconductor device on which wafer-level burn-in test is performed and manufacturing method thereof

A semiconductor device is provided with a clock output control circuit which supplies a long-period clock signal having a period longer than an internal clock signal within an active period and supplies the internal clock signal within a read period subsequent to the active period, a clock transfer circuit which transfers the internal clock signal and the long-period clock signal outputted from the clock output control circuit, a data input/output terminal, and an input/output circuit which outputs read data to the data input/output terminal in synchronization with the internal clock signal having been transferred by the clock transfer circuit.

Such a device is disclosed that includes a terminal, a first voltage generator generating, when activated, a voltage at the terminal and stopping, when deactivated, generating the voltage, and a second voltage generator generating, when activated, the voltage at the terminal and stopping, when deactivated, generating the voltage. The first voltage generator being configured to be activated in response to a first control signal taking an active level and deactivated in response to the first control signal taking an inactive level, and the second voltage generator being configured to be activated in response to each of the first control signal and a second control signal taking an active level and deactivated in response to at least one of the first and second control signal taking an inactive level.

Semiconductor device having plural internal voltage generating circuits and method of controlling the same

To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like.

Semiconductor device having data input/output unit connected to bus line

When a redundancy circuit is fully used and a further defect is present, an irreparable-state signal is produced. When the irreparable-state signal is produced, a defect is judged. When the irreparable-state signal is not produced, upon testing for quality judgment, extraction of a defective memory cell, programming an address of the defective memory cell into a fuse, and confirmation about whether or not the address is properly programmed are carried out. Quality judgment is possible only by confirming address information of the written address as confirmation after programming into the electric fuse.

Growing community of inventors

Tokyo, Japan

Takuyo Kodama