Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Nitto Kasei Co., Ltd.

Takuya Yasui

Keiichi Kurokawa

Masahiko Toyonaga

Junichi Shimada

Fumihiro Kimura

Tsutomu Fujii

Hiromasa Fukazawa

Yoichi Matsumura

Nobuyuki Iwauchi

Takeya Fujino

Hidenori Waku

Hirofumi Miyashita

Tatsuo Gou

Takako Ohashi

Yukiji Hashimoto

Hirofumi Taguchi

Satoshi Kobayashi

Takashi Matsuki

Takayuki Araki

Hitoshi Kitamura

Nagato Oka

Motomichi Ito

A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.

Semiconductor device and semiconductor device layout designing method

Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.

Method for designing semiconductor integrated circuits having air gaps.

An automatic layout method of a semiconductor integrated circuit includes an initial arranging step for initially arranging a logic cell which constitutes the logic circuit; a placement base circuit optimizing step for applying a margin of a constant length to a wiring line length obtained from a placement so as to improve timing; an placement change restriction calculating step for calculating a placement change restriction corresponding to the margin of the constant length; and an incremental arranging step in which when a logic cell placement of a corrected logic circuit is improved, a placement improvement having the placement change restriction calculated based upon the placement change restriction calculating step is carried out.

Automatic layout method of semiconductor integrated circuit

In design of particularly large-scale, complicated semiconductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj&plus;Wmax&plus;T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj&minus;Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

Delay analysis method and design assist apparatus of semiconductor circuit

In design of particularly large-scale, complicated semi-conductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj&plus;Wmax&plus;T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj&minus;Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

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Osaka, Japan

Takuya Yasui