Preferred Networks, Inc.

Takuya Yamauchi

Kohei Takahashi

Hiroya Kaneko

One aspect of the present disclosure relates to an arithmetic processor including a detection unit that detects instruction information, wherein an instruction including a processing instruction to be performed after completion of DMA (Direct Memory Access) in a DMA request instruction is described in the instruction information and a data processing unit that uses data transferred by the DMA request instruction to execute an operation corresponding to the processing instruction based on the instruction information detected by the detection unit.

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Saitama, Japan

Takuya Yamauchi