Sanyo Electric Co., Ltd.

Takuya Suzuki

Shuichi Kikuchi

Eiji Nishibe

Yumiko Akaishi

Yuji Tsukada

Shinya Mori

Yuichi Watanabe

Nobuyuki Takai

The invention provides a semiconductor device with a bonding pad made of a wiring layer including aluminum and its manufacturing method that enhance the yield of the semiconductor device. The method of manufacturing the semiconductor device of the invention includes removing a portion of an antireflection layer (e.g. made of a titanium alloy) formed on an uppermost second wiring layer (e.g. made of aluminum) on a semiconductor substrate by etching, forming a passivation layer covering the antireflection layer and a portion of the second wiring layer where the antireflection layer is not formed and having an opening exposing the other portion of the second wiring layer, and dividing the semiconductor substrate into a plurality of semiconductor dice by dicing. These processes can prevent the antireflection layer from being exposed in the opening, and this can prevent a component of the second wiring layer from being eluted due to cell reaction between the second wiring layer and the antireflection layer as has been seen in the conventional art.

Semiconductor device with passivation layer covering wiring layer

A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the source-drain regions is smaller than at least a diffusion region width of the drain side.

Semiconductor device with source and drain regions

A semiconductor device has a gate electrode formed extending on a first and second gate insulation films formed on P type semiconductor substrate, an N+ type source region adjacent to one end of the gate electrode, an N&#x2212; type drain region facing said source region through a channel region, having high impurity concentration peak at a position of the predetermined depth at least in said substrate under said first gate insulation film, and formed so that high impurity concentration becomes low at a region near surface of the substrate, an N&#x2212; type drain region formed so as to range to the N&#x2212; type drain region, an N+ type drain region separated from the other end of said gate electrode and included in said N&#x2212; type drain region, and an N type layer formed so as to span from one end portion of said first gate insulation film to said N+ type drain region.

Semiconductor device and method of manufacturing the same

A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N&minus; type drain region formed so as to be adjacent to the gate electrode, a high concentration N&plus; type drain region separated from the other end of said gate electrode and included in said low N&minus; type drain region, and a middle concentration N type layer at a region spanning at least from said gate electrode to said high concentration N&plus; type drain region, and formed so that impurity concentration becomes low at a region near the gate electrode.

Semiconductor device for improving sustaining voltage

Semiconductor device manufacturing using one element separation film

A semiconductor device has a gate electrode formed on P type semiconductor substrate through a gate insulation film, a low concentration N&minus; type drain region formed so as to be adjacent to the gate electrode, a high concentration N&plus; type drain region separated from the other end of said gate electrode and included in said low N&minus; type drain region, and a middle concentration N type layer having high impurity concentration peak at a position of the predetermined depth in said substrate at a region spanning at least from said gate electrode to said high concentration N&plus; type drain region, and formed so that high impurity concentration becomes low at a region near surface of the substrate.

LDD high voltage MOS transistor

To enhance the withstand voltage of an LD MOS transistor, a method of fabricating a semiconductor device according to the invention is characterized in that a process for forming a drift region is composed of a step for implanting phosphorus ions and arsenic ions different in a diffusion coefficient into the superficial layer of a substrate, a step for forming a selective oxide film (a first gate insulating film) 9A and an element isolation film 9B by selective oxidation and diffusing the phosphorus ions and the arsenic ions and a step for implanting and diffusing boron ions, and in that in the step for forming the selective oxide film 9A and the element isolation film 9B by selective oxidation in a state in which an oxide film and a polycrystalline silicon film are laminated on the substrate, only a drift region formation region is selectively oxidized in a state in which the polycrystalline silicon film is removed.

Growing community of inventors

Saitama, Japan

Takuya Suzuki