Sharp Kabushiki Kaisha Corporation

Takuya Otabe

Yukio Tamai

Masaya Nagata

Satoshi Hikida

Hisashi Yonemoto

The high-withstand voltage MOSFET comprises a trench portion formed at the high-withstand voltage active region on a semiconductor substrate, two polysilicon layers formed on the high-withstand voltage active region on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region, two impurity diffusion drift layers formed on both sides of the trench portion by implanting an impurity of the conductivity type opposite to the high-withstand voltage active region in the surface of the high-withstand voltage active region under the polysilicon layers, and a gate electrode formed through a gate oxide film on bottom and side surfaces of the trench portion and end surfaces and upper surfaces of adjacent regions of the polysilicon layers close to the trench portion, and source and drain regions are formed in the two polysilicon layers excluding the adjacent regions covered with the gate electrode.

Semiconductor device comprising high-withstand voltage MOSFET and its manufacturing method

In the case where a variable resistive element, which is made of a variable resistor provided between a first and second electrodes, and of which the electrical resistance varies by applying a voltage pulse between the two electrodes, is applied to a resistance nonvolatile memory, there is a range of the resistance value of the variable resistive element in a low resistance state where the nonvolatile memory can operate normally. In the conventional manufacturing method the resistance value of the variable resistive element is too low, therefore, it can not be controlled within a desired range of the resistance value. A step of carrying out of a reduction process is provided at any point after the step of forming a variable resistor material as a film, it has thereby become possible to increase the resistance value of the variable resistive element, which is too low in the conventional method.

Manufacturing method for variable resistive element

A semiconductor device fabrication method comprises (1) forming a patterned mask layer on an oxide layer of a Mn-containing perovskite type oxide; (2) heat-treating the oxide layer; and (3) patterning the oxide layer with an etching solution containing at least one of hydrochloric acid, sulfuric acid, and nitric acid after the heat treatment of the oxide layer.

Semiconductor device fabrication method

On a silicon substrate, there are formed a silicon oxide, an adhesion layerconsisting of TiO, a lower electrodeconsisting of Pt, a ferroelectric thin film, and an upper electrodeconsisting of Pt. A portion of the ferroelectric thin film adjacent to the upper electrodeis formed from a compound with a composition formula of SrBi(TaNb)Owhere x=0.7. A compound with a value x in the composition formula being greater than 0.7 is used for the portion of the ferroelectric thin film adjacent to the upper electrode, so as to generate an appropriate number of grain boundaries on the surface of the ferroelectric film, the grain boundaries enabling implementation of anchoring effect between the ferroelectric filmand the upper electrode, thereby achieving prevention of exfoliation of the upper electrodefrom the ferroelectric film. Therefore, the semiconductor memory device is free from exfoliation of the upper electrode film from the dielectric film and has a good yield.

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Fukuyama, Japan

Takuya Otabe