Micron Technology Incorporated

Mitsubishi Electric Corporation

Waseda University

Takuya Nakanishi

Toru Ishikawa

Shinji Bessho

Takumi Nasu

Yutaka Ito

Zer Liang

Minari Arai

Yoshinori Fujiwara

Tomokazu Sakashita

Masahiro Yanagisawa

Ryota Kondo

Tetsuya Osaka

Takaaki Takahara

Yusuke Higaki

Hiroyasu Iwabuki

Mikiko Saito

Kiyotake Sakurai

Hiroto Mizutani

Hidehito Yoshida

Tim Cowles

Mariko Shiozaki

Naonobu Shimamoto

Koichiro Ito

Yuan Hsuan Jhang

Kenya Adachi

An apparatus that includes a memory cell array, an I/O terminal supplied with an original write data in a normal operation, a compression logic circuit configured to generate a compressed test data in a test operation based on a test read data read from the memory cell array, and a syndrome generator configured to generate a first syndrome based on the original write data in the normal operation and generate a second syndrome based on the compressed test data in the test operation.

Semiconductor device having syndrome generator

An inverter and power transmission coils are connected such that currents flow in opposite directions to each other when selection switches of respective power transmission coils adjacent to each other, out of a plurality of power transmission coils disposed in the movement direction of a mobile body, are caused to be conductive. The difference in currents flowing in the opposite directions is measured, and compared with a threshold, whereby whether or not a power reception coil mounted to the mobile body is present above the power transmission coil can be determined.

Power transmission device

Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Apparatuses, systems, and methods for error correction

A wireless power feeding system includes: a power transmission circuit portion for converting DC power supplied from a main power supply, to AC power, and for supplying the AC power to a power-transmission-side coil; input power control means for controlling the AC power to be supplied to the power-transmission-side coil; a power-reception-side coil which is magnetically coupled with the power-transmission-side coil and to which AC power is transmitted from the power-transmission-side coil through magnetic energy accumulated between the power-reception-side coil and the power-transmission-side coil; a power reception circuit including a rectifier for converting the AC power transmitted to the power-reception-side coil, to DC, and a power-reception-side DC/DC converter; and power reception circuit control means for controlling rectifier output voltage to be a maximum efficiency voltage at which power transmission efficiency becomes maximum.

Wireless power feeding system and power reception device

An error correction code (ECC) circuit receives a plurality of data hits and provides a one or more parity bits. The parity bits are used to locate and/or correct errors in the data bits. The ECC circuit splits the plurality of data bits into multiple portions and then processes these portions sequentially to generate preliminary parity bits. Once the portions of the data have been sequentially processed, the preliminary parity bits are combined to generate the parity bits.

Apparatuses, systems, and methods for multi-pump error correction

Apparatuses, systems, and methods for error correction for selected bit pairs. A memory device may include an error correction code (ECC) circuit which may receive data bits as part of a read or write operation and generate parity bits based on the data bits. The parity bits may be used to locate and correct errors in the data bits. The parity bits may be generated based on a syndrome value. Each of the individual data bits may be associated with a syndrome value. In addition, some selected pairs of data bits may also be associated with a syndrome value. This may allow the ECC circuit to correct errors in individual data bits or in one of the selected pairs of data bits. In some embodiments, the selected pairs may represent adjacent memory cells along a word line.

Apparatuses, systems, and methods for error correction of selected bit pairs

An output terminal of a contact type charger connected to an AC power supplyand being for boosting or stepping down an input voltage, and an output terminal of a non-contact type charger for receiving power in a non-contact manner are connected to an input terminal of a DC/DC converter via an integrated bus, a DC link capacitor is connected between an AC/DC converter and an isolated DC/DC converter included in the contact type charger, an integrated capacitor is connected to the integrated bus, and a control circuit adjusts a DC voltage of the DC link capacitor or the integrated capacitor such that at least one of power losses or a total power loss of the contact type charger, the non-contact type charger, and the DC/DC converter is reduced.

Power conversion device having a configuration for simultaneous wired and wireless charging

A first converter performs power conversion and outputs AC power. The AC power outputted from the first converter is supplied to a first coil. The first coil is magnetically coupled with a second coil, and the AC power is transmitted from the first coil to the second coil. A second converter is connected to the second coil, and converts the AC power transmitted to the second coil to DC power and supplies the DC power to a load. A first control unit controls the first converter so as to alternately switch between a first state of outputting rectangular wave voltage which cyclically changes and a second state of outputting constant reference voltage, on the basis of required power of the load.

Non-contact power supply system and power transmission device

Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

Error correction code circuits having one-to-one relationships with input/output pads and related apparatuses and methods

Disclosed herein is an apparatus that includes a command shifter configured to receive a command pulse and generate a plurality of first command shifted pulses in parallel, wherein each of the plurality of first command shifted pulses has the same width as the command pulse and the plurality of first command shifted pulses have different phases from each other, and a command filter configured to determine if a plurality of second command shifted pulses are generated correspondingly to the plurality of first command shifted pulses or not generated responsive to pulse overlapping among at least ones of the plurality of first command shifted pulses.

Command filter filtering command having predetermined pulse width

Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

Semiconductor device performing row hammer refresh operation

In a non-contact power feeding system for transmitting/receiving power, by magnetic coupling, between a coil connected to a transmitting side DC/AC conversion circuit and a coil connected to a receiving side AC/DC conversion circuit so as to supply power from a power supply to a load, voltage control for the load is performed by the transmitting side DC/AC conversion circuit, and control of current that flows to a capacitor connected to an output side of the receiving side AC/DC conversion circuit is performed by the receiving side AC/DC conversion circuit. Accordingly, coil to coil efficiency in a case of low load can be enhanced without the need for any additional circuit.

Non-contact power feeding system and power reception device

Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

In some examples, a memory device may include an internal synchronization circuit that provides for double data rate operation of the memory device when external single data rate signals are provided to the memory device. The external signals may be command and/or address signals provided by an external testing circuits in some examples. The internal synchronization circuit may latch and/or delay at least some of the external signals such that different external commands are provided at the rising and falling edges of the clock signal of the memory device. The memory device may latch the external signals at both the rising and falling edges of the clock signal for double data rate operation of the memory device.

Growing community of inventors

Tsukuba, Japan

Takuya Nakanishi