Nec Corporation

N.e. Chemcat Corporation

Takuya Katoh

Hiroshi Shiba

Kenji Okada

Osamu Kudoh

Akito Takayama

A three-way catalyst for purifying exhaust including noble metal components, enables sintering of the noble metal to be suppressed even at high temperature, enables carbon monoxide (CO), hydrocarbons (HC), and nitrogen oxides (NOx) to be removed and a method for purifying exhaust gas. A carrier having a honeycomb structure is coated with two or more layers of the catalyst compositions, an upper layer including a heat resistant inorganic oxide supporting Pd and a La-containing oxide, a lower layer including a heat resistant inorganic oxide supporting Rh. The content of La in terms of LaOis 9.6 g/L to 23 g/L, the content of Ce in terms of CeOis 5 g/L to 20 g/L, and the content of Ba in terms of BaO is 1.2 g/L or less per unit volume of the honeycomb structure.

Three-way catalyst for purifying gasoline engine exhaust gas

Active matrix TFT elements array in which the number of production steps is not increased and the high production yield can be achieved. A semiconductor film is formed by patterning in an elongated island shape between pixel electrodes disposed neighboring to each other in the direction of drain lines to provide a protrusion to prevent shorting across the pixel electrodes even if photoresist film residuals are produced.

Active matrix type TFT elements array having protrusion on gate lines

Thin film transistor elements are disposed on a substrate in a matrix form. The thin film transistor element includes a source electrode, a drain electrode, isolated layer of a semiconductor layer and a gate insulating film, and a gate electrode. Drain wires and gate wires are provided on the substrate, and they are connected to the drain electrode and source electrode, respectively. Each of intersections of the drain wires and the gate wires has another isolated layer of a semiconductor layer and a gate insulating film. Each of the drain wires has an isolated conductive film which is made of the same material as the gate wires. The conductive film is formed to be contact with each of the drain wires so as to electrically support the drain wires each. Pixel electrodes are provided on the substrate. Each of the pixel electrodes preferably has a overlapping section with the adjacent gate wire and an auxiliary capacitor with another isolated layer of a semiconductor and a gate insulating film is formed on the overlapping section. Any leakage current do not flow between the thin film transistor elements in this thin film transistor elements array because the isolated layers including a semiconductor layer are provide in island form.

Thin film transistor element array

A semiconductor device that has a feature in the spatial relationship between the wiring in a multi-level wiring and the intermediate insulating films. In the lower part of the second and/or subsequent levels of wiring there exist intermediate insulating films that have a pattern which is the same as the pattern of the wiring. Because of this arrangement, the intermediate insulating film does not exist between the wiring on the same level. The first structure of the multi-level wiring has the intermediate insulating films formed in wall-like shape, with the lower end of the intermediate insulating films reaching an underlying insulating layer formed on the surface of the semiconductor substrate. The second structure of the multi-level wiring is a quasi air gap metallization structure. As a result of realization of such structures, in the semiconductor device according to the present invention, the parasitic capacitance due to the coupling capacitances between the wiring can be reduced compared with a semiconductor device that has a structure in which the spaces between the wiring are filled with the intermediate films.

Semiconductor device having multi-level wiring

In a semiconductor device, an inter-level insulating film is formed at solid crossing points between upper level interconnections and lower-level interconnections, excepting via hole portions. This means that mechanical support between interconnection levels is given by solid crossing points between interconnections. For this, a semiconductor device having high durabilities against thermal and mechanical impacts can be obtained. Further, since inter-level regions other than the solid crossing points are made vacant to form a cavity, coupling capacity can be reduced to 1/3 to 1/2 of an ordinary multilevel interconnections wherein inter-level regions are fully filled with an inter-level insulating film.

Growing community of inventors

Tokyo, Japan

Takuya Katoh