Kabushiki Kaisha Toshiba

Takuya Kano

Hiroshi Sakai

Hiroo Hayashi

Yoshio Masubuchi

Addresses of all of dirty blocks of a cache memory are, by an update address registering section, stored in one of plural regions of an update address memory. When a certain cache block is brought to a dirty state and then suspended from the dirty state, the update address removing section removes the address from the region. When cache flush is performed, a flush executing section sequentially fetches the addresses of the dirty blocks from each region to issue, to the system bus, a command for writing-back data indicated by the address into the main memory so that the contents of all of the a dirty block are written-back into the main memory. Therefore, the cache flush apparatus according to the present invention is able to shorten time required to perform the cache flush procedure and to improve the performance of a computer system having the cache flush apparatus.

Cache flush apparatus and computer system having the same

A novel checkpoint acquisition accelerating apparatus is disclosed. When data are updated on a cache memory, a before-image acquiring section acquires the update address and the previous data and stores them in a before-image storing section. A cache flush executing section issues to a system bus a bus command requesting the contents of the updated cache block to be written-back to a main memory using all the addresses stored in the before-image storing section. A main memory restoring section, on the other hand, issues bus command requesting all the previous data stored in the before-image storing section to be updated and written in the main memory on last-in first-out basis. As a result, a checkpoint acquisition accelerating apparatus is realized which is capable of easily realizing the checkpoint and recovery function in a computer including at least a standard uniprocessor.

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Tokyo, Japan

Takuya Kano